3-4
Intel® PXA27x Processor Family
Optimization Guide
System Level Optimization
Note:
The Intel XScale® Microarchitecture page-attributes are different than the Intel® StrongARM*
SA-1110 Microprocessor (SA-1110). The SA-1110 code may behave differently on PXA27x
processor systems due to page attribute differences.
describes the differences in the
encoding of the C and B bits for data accesses. The main difference occurs when cacheable and
nonbufferable data is specified (C=1, B=0); the SA-1110 uses this encoding for the mini-data cache
while the Intel XScale® Microarchitecture uses this encoding to specify write-through caching.
Another difference is when C=0, B=1, where the Intel XScale® Microarchitecture coalesces stores
in the write buffer; the SA-1110 does not.
3.3
Optimizing for Instruction and Data Caches
Cache locking allows frequently used code to be locked in the cache. Up to 28 cache lines can be
locked in a set, while the remaining four entries still participate in the round robin replacement
policy.
3.3.1
Increasing Instruction Cache Performance
The performance of the PXA27x processor is highly dependent on the cache miss rate. Due to the
complexity of the processor fetching instructions from external memory can have a large latency.
Moreover, this cycle penalty becomes significant when the Intel XScale® core is running much
faster than external memory. Executing non-cached instructions severely curtails the processor's
performance so it is important to do everything possible to minimize cache misses.
1 0
(Mini-data
cache)
—
—
—
Cache policy is determined by
MD field of Auxiliary Control
register
††
1 1
Y
Y
Write-back
Read/Write
Allocate
†
Normally, "bufferable" writes can coalesce with previously buffered data in the same address range
††
Refer to
Intel XScale® Core Developer’s Manual
and the
Intel® PXA27x Processor Family Developer’s
Manual
for a description of this register.
Table 3-5. Data Cache and Buffer operation comparison for Intel® SA-1110 and Intel XScale®
Microarchitecture, X=0
Encoding
SA-1110 Function
Intel XScale® Microarchitecture Function
C=1,B=1
Cacheable in data cache; store misses can
coalesce in write buffer
Cacheable in data cache, store misses can
coalesce in write buffer
C=1,B=0
Cacheable in mini-data cache; store misses
can coalesce in write buffer
Cacheable in data cache, with a write-through
policy. Store misses can coalesce in write
buffer
C=0,B=1
Noncacheable; no coalescing in write buffer,
but can wait in write buffer
Noncacheable; stores can coalesce in the write
buffer
C=0,B=0
Noncacheable; no coalescing in the write
buffer, SA-110 stalls until this transaction is
done
Noncacheable, no coalescing in the write
buffer, Intel XScale® Microarchitecture stalls
until the operation completes.
Table 3-4. Data Cache and Buffer Behavior when X = 1 (Sheet 2 of 2)
C B
Cacheable?
Load Buffering
and Write
Coalescing?
Write Policy
Line Allocation
Policy
Notes
Summary of Contents for PXA270
Page 1: ...Order Number 280004 001 Intel PXA27x Processor Family Optimization Guide April 2004...
Page 10: ...x Intel PXA27x Processor Family Optimization Guide Contents...
Page 20: ...1 10 Intel PXA27x Processor Family Optimization Guide Introduction...
Page 30: ...2 10 Intel PXA27x Processor Family Optimization Guide Microarchitecture Overview...
Page 48: ...3 18 Intel PXA27x Processor Family Optimization Guide System Level Optimization...
Page 114: ...5 16 Intel PXA27x Processor Family Optimization Guide High Level Language Optimization...
Page 122: ...6 8 Intel PXA27x Processor Family Optimization Guide Power Optimization...
Page 143: ...Intel PXA27x Processor Family Optimization Guide Index 5 Index...
Page 144: ......
