Intel PXA270, Optimization Manual

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Intel® PXA27x Processor Family Optimization Guide 4-49
Intel XScale® Microarchitecture & Intel® Wireless MMX™ Technology Optimization
4.10.2.4 Coprocessor Interface Pipeline
The coprocessor interface pipeline also contains buffering to allow multiple outstanding
MRC/MRRC operations. The coprocessor interface pipeline can continue to accept MRC and
MRRC instructions every cycle until its buffers are full. Currently there is sufficient storage in the
buffer for either four MRC data values (32-bit) or two MRRC data values (64-bit). Table 4-23
shows a summary of the resource availability delay for the Coprocessor interface.
There is also an interaction between TMRC/TMRRC and any instructions in the core that utilize
the MAC unit of the core. For optimum performance, the MAC unit in the core should not be used
adjacent to TMRC instructions as they both share the route back to the core register file.
4.10.2.5 Multiple Pipelines
The WSAD, TMIA, TMIAph and TMIAxy instructions execute in both the main Execution
pipeline and the Multiplier pipeline. The instruction executes one cycle in the Execution pipeline
and the rest in the Multiplier pipeline. The WSAD, TMIA, TMIAph, TMIAxy instructions will
always issue without stalls to the Execution pipeline (see Section 4.10.2.1 ). The availability of the
multiplier pipeline depends on a previous instruction that was using the multiply resource. If the
previous instruction was a TMIA, there is an effective resource availability of two cycles.
Table 4-23. Resource Availability Delay for the Coprocessor Interface Pipeline
Instructions Delay(Clocks) Condition
TMRC 1 Buffer Empty
TMRC 2 Buffer Full
TMRRC 1 Buffer empty
TMRRC 2 Buffer Full