2-8
Intel® PXA27x Processor Family
Optimization Guide
Microarchitecture Overview
Wireless MMX™ Technology stalls Intel XScale® Microarchitecture. Note that control hazards
are detected in the Intel XScale® Microarchitecture, and a flush signal is sent from the core to the
Intel® Wireless MMX™ Technology.
2.3.1.3
X1 Stage
The X1 stage is also known as the execution stage, which is where most instructions begin being
executed. All instructions are conditionally executed and that determination occurs at the X1 stage
in the Intel XScale® Microarchitecture. A signal from the core is required to indicate whether the
instruction being executed is committed. In other words, an instruction being executed at the X1
stage may be canceled by a signal from the core. This signal is available to the Intel® Wireless
MMX™ Technology in the middle of the X1 pipe stage.
2.3.1.4
X2 Stage
The Intel® Wireless MMX™ Technology supports saturated arithmetic operations. Saturation
detection is completed in the X2 pipe stage.
If the Intel XScale® Microarchitecture detects exceptions and flushes in the X2 pipe stage, Intel®
Wireless MMX™ Technology also flushes all the pipeline stages.
2.3.1.5
XWB Stage
The XWB stage is the last stage of the X pipeline, where a final result calculated in the X pipeline
is written back to the register file.
2.3.2
Multiply Pipeline Thread
2.3.2.1
M1 Stage
The M pipeline is separated from the X pipeline. The execution of multiply instructions starts at the
beginning of the M1 stage, which aligns with the X1 stage of the X pipeline. While the issue cycle
for multiply operations is one clock cycle, the result latency is at least three cycles. Certain
instructions such as TMIA, WMAC, WMUL, WMADD spend two M1 cycles since the Intel®
Wireless MMX™ Technology has only two 16x16 multiplier arrays. Booth encoding and first-
level compression occur in the M1 pipe stage.
2.3.2.2
M2 Stage
Additional compression occurs in the M2 pipe stage, and the lower 32 bits of the result are
calculated with a 32 bit adder.
2.3.2.3
M3 Stage
The upper 32 bits of the result are calculated with a 32-bit adder.
2.3.2.4
MWB Stage
The MWB stage is the last stage of the M pipeline, which is where a final result calculated in the M
pipeline is written back to the register file.
Summary of Contents for PXA270
Page 1: ...Order Number 280004 001 Intel PXA27x Processor Family Optimization Guide April 2004...
Page 10: ...x Intel PXA27x Processor Family Optimization Guide Contents...
Page 20: ...1 10 Intel PXA27x Processor Family Optimization Guide Introduction...
Page 30: ...2 10 Intel PXA27x Processor Family Optimization Guide Microarchitecture Overview...
Page 48: ...3 18 Intel PXA27x Processor Family Optimization Guide System Level Optimization...
Page 114: ...5 16 Intel PXA27x Processor Family Optimization Guide High Level Language Optimization...
Page 122: ...6 8 Intel PXA27x Processor Family Optimization Guide Power Optimization...
Page 143: ...Intel PXA27x Processor Family Optimization Guide Index 5 Index...
Page 144: ......
