Intel® PXA27x Processor Family
Optimization Guide
3-1
System Level Optimization
3
This chapter describes relevant performance considerations that developers and system designers
should be aware of to efficiently use the Intel® PXA27x Processor Family (PXA27x processor).
3.1
Optimizing Frequency Selection
The PXA27x processor offers a range of combinations of core, system bus and memory clock
speed. The run mode frequency and derived system bus and memory controller frequencies affect
the latency and throughput of external memory interfaces.
Memory latencies depend on the run mode frequency, because a higher run mode frequency
improves performance for memory bound applications. The core clock speed is indicated by the
run frequency, or (if CLKCFG[T] is set) by the turbo frequency. This value is most significant for
computationally bound applications. For a memory bound application, a processor operating in
333-MHz run mode might perform better than a processor operating in 400-MHz turbo mode using
only a 200-MHz run mode frequency. The clock frequency combination should be chosen to fit the
target application mix. Possible frequency selections are listed in the clocks and power manager
section of the
Intel® PXA27x Processor Family Developer’s Manual
.
3.2
Memory System Optimization
3.2.1
Optimal Setting for Memory Latency and Bandwidth
Because the PXA27x processor has a multi-transactional internal bus, there are latencies involved
with accesses to and from the Intel XScale® core. The internal bus, also called the system bus,
allows many internal operations to occur concurrently such as LCD, DMA controller and related
data transfers.
and
list latencies and throughputs associated with different
frequencies. The throughput reported in the tables is only measuring load
Table 3-1. External SDRAM Access Latency and Throughput for Different Frequencies
(Silicon Measurement Pending)
Core Clock
Speed (MHz)
(up to)
Run Mode
Frequency (MHz)
(up to)
System Bus Clock
Speed (MHz)
(up to)
Memory
Clock Speed
(MHz)
(up to)
Memory
Latency
(core cycles)
Load
Throughput
from Memory
(MBytes/
Sec)
104
104
104
104
17
205
208
208
208
104
21
326
312
208
208
104
30
343
Summary of Contents for PXA270
Page 1: ...Order Number 280004 001 Intel PXA27x Processor Family Optimization Guide April 2004...
Page 10: ...x Intel PXA27x Processor Family Optimization Guide Contents...
Page 20: ...1 10 Intel PXA27x Processor Family Optimization Guide Introduction...
Page 30: ...2 10 Intel PXA27x Processor Family Optimization Guide Microarchitecture Overview...
Page 48: ...3 18 Intel PXA27x Processor Family Optimization Guide System Level Optimization...
Page 114: ...5 16 Intel PXA27x Processor Family Optimization Guide High Level Language Optimization...
Page 122: ...6 8 Intel PXA27x Processor Family Optimization Guide Power Optimization...
Page 143: ...Intel PXA27x Processor Family Optimization Guide Index 5 Index...
Page 144: ......
