43
PCI-X Layout Guidelines
6.2
PCI General Layout Guidelines
For acceptable signal integrity with bus speeds up to 133 MHz it is important to PCB design layout
to have controlled impedance.
•
Signal trace velocity needs to be roughly 150 – 190 ps/inch
•
The following signals have no length restrictions: P_INT[D:A], S_INT[D:A] and
TCK
,
TDI
,
TDO
,
TMS
and
TRST#
6.3
PCI-X Topology Layout Guidelines
The
PCI-X Addendum to the PCI Local Bus Specification,
Revision 1.0a, recommends the
following guidelines for the number of loads for your PCI-X designs. Any deviation from these
maximum values requires close attention to layout with regard to loading and trace lengths.
Table 7.
PCI-X Slot Guidelines
Frequency
Maximum Loads
Maximum Number of Slots
66 MHz
8
4
100 MHz
4
2
133 MHz
2
1
Summary of Contents for 80331
Page 1: ...Intel 80331 I O Processor Design Guide March 2005 Order Number 273823 003 ...
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Page 122: ...122 Intel 80331 I O Processor Design Guide Memory Controller ...
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