Intel 80331, Design Manual

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Intel® 80331 I/O Processor Design Guide
Memory Controller
7.5.4.2 DDRII 400 Embedded Clock Routing Recommendations
This section lists the recommendations for the DDR II 400 clock signals. Refer to Figure 57 and
Table 68 for a description of the segment lengths and matching requirements Table 69 provides the
guidelines from PLL to SDRAM.
Table 68. DDRII 400 Embedded Clock Routing Recommendations
Parameter Routing Guideline
Reference Plane Route over unbroken ground plane
Preferred Topology Microstrip or Stripline routed differentially
Breakout Trace Width and Spacing 5 mils x 5 mils.
Trace Spacing
• 5 mil spacing acceptable between pin escapes
and breakout regions.
• 5 mils for clock differential pairs (intra-pair),
• >20 mils between other signals.
Trace Impedance
Differential impedance of 100 ohms +/- 15%
Refer to Figure 57
Trace Details
Route as differential pair with differential impedance of
100 ohms.
Figure 57
Overall Trace Length
2.0”min to 10.0” max; refer to figures and tables that
follow for line segment lengths and topology.
DQS Length Matching:
• Within differential clock signals +/- 0.0250” within pairs (intra-pair)
Overall clock correlation with other signals
• All DQ/DQS groups matching needs to be
matched /- 1” of the clock signals.
• Address/Command/Control lengths from 80331
ball to the register needs to be matched /-
1” of the clock signals
Series Termination No series termination for buffered memory
Parallel Termination 100 ohms
Routing Guideline 1 Maximum of 2 via/layer change for differential clocks.
Routing Guideline 2
Route clock signal as differential pair with target
differential impedance of 100 ohms and single ended
impedance of 50 ohms with ground referenced strip
line only.