120
Memory Controller
7.6
DDR Signal Termination
This section provides suggested guidelines for layout of the DDR termination resistors:
•
Place a 1.25 V termination plane for DDR or a 0.9V termination plane for DDR II 400 on the
top layer or one of the inner layers, just beyond the DIMM connector for DDR.
•
The
V
TT
island must be at least 50 mils wide.
•
Use this termination plane to terminate all DIMM signals, using the one termination resistor
per signal.
•
Decouple the
V
TT
plane using one 0.1
µ
F decoupling capacitor per two termination resistors.
•
Each decoupling capacitor must have at least two vias between the top layer ground fill and the
internal ground plane.
•
In addition, place one 10
µ
F or larger (100
µ
F suggested) Tantalum capacitor on each end of
the termination island for bulk decoupling.
•
provides an example of how to route the termination resistors.
Figure 60.
Routing Termination Resistors (top view)
B2820-01
GND Plane
< = 50 mil wide
Rp
DDR - 1.25 V / DDR II - 0.9 V Plane
1.0 F Capacitor
per two resistors
10.0 F Capacitor
2 Vias per Capacitor
DIMM
Note: Rp = Parallel Termination Resistor
Summary of Contents for 80331
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