Intel 80331, Design Manual

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Intel® 80331 I/O Processor Design Guide
Terminations
3.1 Analog Filters
The following section describes filters needed for biasing PLL circuitry.
3.1.1 V
CCPLL
Pin Requirements
To reduce clock skew, the V
CCPLL
balls for the Phase Lock Loop (PLL) circuit are isolated on the
package. The lowpass filter, as shown in Figure 7 reduces noise induced clock jitter and its effects on
timing relationships in system designs. The node connecting V
CCPLL
and the capacitor must be as
short as possible. The Figure 7 filter circuit is recommended for each of the Four PLL pairs: V
CCPLL1
- V
SSA1,
V
CCPLL2
- V
SSA2,
V
CCPLL4
- V
SSA4
and V
CCPLL5
- V
SSA5
pairs.
The following notes list the layout guidelines for this filter.
•
4.7 µH (Inductor)
— L must be magnetically shielded
— ESR: max < 0.4
Ω
— rated at 45mA
— An example of this inductor is TDK part number MLZ2012E4R7P.
•
22 µF (Capacitor)
— ESR: max < 0.4
Ω
— ESL < 3.0nH
— Place 22 µF capacitor as close as possible to package pin.
•
0.5 ohm 1% (Resistor)
— 1/16W 6.3V
•
0.5 ohm 1% resistor must be placed between V
CC
and L. The resistor rating is 1/16W.
•
Route V
CCPLL
[1-5] and V
SSA
[1-5] as differential traces.
•
V
CCPLL
[1-5] and V
SSA
[1-5] traces must be ground referenced (No V
CC
references).
•
Maximum total board trace length = 1.2”.
•
Minimum trace space to other nets = 30 mils.
•
The 1.5 V supply regulator used for the PLL filter must have less than
+/- 3
% tolerance.
•
Note: V
SSA1
, V
SSA2,
V
SSA4 and
V
SSA5
pins must not be connected to ground.
Figure 7. V
CCPLL
Configuration
Intel®
I/O Proc es sor
V CCPLL
V SSA
1.5 V
Board Route
Traces
Breakout Trac es
Beneath BGA
Board Trac e:
Trace w idth > 25 mils
Trac e Spac ing < 10 mils
Trac e Length < 600 mils
Breakout Trac e:
Trac e w idth > 6 mils
Trace Spacing < 6 mils
Trac e Length < 600 mils
4.7 uH <25%
22 uF <20%
Note: Do Not connect V SSA pins to ground
0.5 ohms , 1%