1-9
1
1.6
DIGITAL SIGNAL SPECIFICATIONS
The Digital I/O signals have the following specifications:
1.6.1
Data Lines
Number
32 with internal 33 kohm pullups to + 5 Vdc
Input
High
>=2.4 Vdc or open circuit
Levels
Low
< 0.5 Vdc at 200
µ
A
Max
5.5 Vdc
Output
High
> 3.0 Vdc with 3 mA source
Levels
> 2.0 Vdc with 24 mA source
Low
< 0.55 Vdc with 48 mA sink
1.6.2
Monitored Digital Inputs
If the first sixteen Digital I/O lines (CH1-16) are configured as inputs, CH1-
15 are sampled at an approximate 1 kHz rate and the values placed in the
Questionable Register in the IEEE-488.2 Status Reporting Structure. Signal
changes may be used to generate a Service Request. The digital input lines
are reported at the following bits in the Questionable Register and may be
read as normal inputs.
CH#
- 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1.6.3
Timing Chart
The digital output lines are initialized to the saved configuration values at
the end of the selftest. During the selftest time, the output signals are
tristated and pulled passively high. Figure 1-1 shows the output signal
timing.
Data Lines
Lines tristated
Lines driven
Power turn-on
Tselftest
Tconfig
Figure 1-1 Data Outputs After Power Turn-on
