Byte
Factory
Default
Description
09
04h
PCIe Maximum Link Width: The maximum PCIe link width for
this NVM Subsystem port. This is the expected negotiated link
width that the port link trains to if the platform supports it. A
Management Controller may compare this value with the PCIe
Negotiated Link Width to determine if there has been a PCIe link
training issue.
Value
Definition
0
Reserved
1
PCIe x1
2
PCIe x2
3
Reserved
4
PCIe x4
5-7
Reserved
8
PCIe x8
9-11
Reserved
12
PCIe x12
13-15
Reserved
16
PCIe x16
17-31
Reserved
32
PCIe x32
33-255
Reserved
10
00h
MCTP Support: This field contains a bit vector that specifies the
level of support for the NVMe Management Interface. Bits 7 to 1
are reserved. Bit 0, if set to
1
, indicates that MCTP based
management commands are supported on the PCIe port.
11
01h
Ref Clk Capability: This field contains a bit vector that specifies
the PCIe clocking modes supported by the port.
Bit
Definition
7:04
Reserved
3
Set to
1
if the device automatically
uses RefClk if provided and
otherwise uses SRIS. Otherwise
cleared to
0
.
ES3000 V5 NVMe PCIe SSD
User Guide
B Out-of-Band Management
Issue 07 (2019-03-19)
Copyright © Huawei Technologies Co., Ltd.
209
