Table B-6
NVMe PCIe PortMultiRecord Area
Byte
Factory
Default
Description
00
0Ch
NVMe PCIe Port Record Type ID
01
82h
Bit 7
–
end of list; record format version = 2h
02
0Bh
Record Length (RLEN): This field indicates the length of the
MultiRecord Area in bytes.
03
Impl Spec
Record Checksum: This field is used to give the record data a zero
checksum (i.e., the modulo 256 sum of the record data bytes from
byte offset 05 through the end of this record plus this checksum
byte equals zero).
04
Impl Spec
Header Checksum: This field is used to give the record header a
zero checksum (i.e., the modulo 256 sum of the preceding record
bytes starting with the first byte of the header plus this checksum
byte equals zero.
05
00h
NVMe PCIe Port MultiRecord Area Version Number: This field
indicates the version number of this multirecord. This field shall be
set to zero in this version of the specification.
06
00h
PCIe Port Number: This field contains the PCIe port number. This
is the same value as that reported in the Port Number field in the
PCIe Link Capabilities Register.
07
01h
Port Information: This field indicates information about the PCIe
Ports in the device. Bits 7 to 1 are reserved. Bit 0, if set to
1
,
indicates that all PCIe ports within the device have the same
capabilities (i.e., the capabilities listed in this structure are
consistent across each PCIe port).
08
07h
PCIe Link Speed: This field indicates a bit vector of link speeds
supported by the PCIe port.
Bit
Definition
7:3
Reserved
2
Set to
1
if the PCIe link supports 8.0
GT/s. Otherwise cleared to
0
.
1
Set to
1
if the PCIe link supports 5.0
GT/s. Otherwise cleared to
0
.
0
Set to
1
if the PCIe link supports 2.5
GT/s. Otherwise cleared to
0
.
ES3000 V5 NVMe PCIe SSD
User Guide
B Out-of-Band Management
Issue 07 (2019-03-19)
Copyright © Huawei Technologies Co., Ltd.
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