47
2 System Board - (SiS Chipset) (Part Number: D4051-63001)
Devices on the Processor Local Bus (D4051-63001)
The data cache tags (directory entries used to reference cached memory
pages) are triple-ported to support two data transfers and an inquire cycle
in the same clock cycle. The code cache tags are also triple-ported to
support snooping (a way of tracking accesses to main memory by other
devices) and split line accesses.
Individual pages of memory can be configured as cacheable or non-
cacheable by software or hardware. They can also be enabled and disabled
by hardware or software.
Data Integrity
The processor uses a number of techniques to maintain data integrity. It
employs two methods of error detection:
•
Data Parity Checking
This is supported on a byte-by-byte basis, generating parity bits for data
addresses sent out of the microprocessor. These parity bits are not used
by the external subsystems.
•
Internally
The processor uses functional redundancy checking to provide maximum
error detection of the processor and its interface.
Advanced Power Management
The Advanced Power Management (APM) is a standard, defined by Intel
and Microsoft, for a power-saving mode that is applicable under a wide
range of operating systems. The version APM 1.1 supports the following
modes:
Fully-on, Standby, Suspend,
and
Off
.
The
Suspend
mode is managed at the operating system level only, from the
Windows 95 Start menu. There is no longer the inter-activity between BIOS
Setup
and operating systems, and no longer a “sleep at” item on the
Setup
program menus, to avoid the BIOS from shutting down the system at the
wrong moment.
Summary of Contents for 520 5/XX
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