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2 System Board - (SiS Chipset) (Part Number: D4051-63001)
SiS Chipset
Host/PCI Bridge (SiS 5511 Chip)
The SiS 5511 chip (PCMC) bridges between the host bus and the PCI local
bus. This device integrates cache and memory control functions and
provides bus control functions for the transfer of information between the
micro-processor, cache, main memory and the PCI bus.
The PCMC monitors each cycle initiated by the CPU, and forwards it to the
PCI bus if the CPU cycle does not target the local memory. For the CPU or
the PCI to the local memory cycles, the built-in cache and DRAM controller
assumes the control to the secondary cache, DRAMs, and the
SiS 5512 PCI local data buffer (PLDB).
The main features supported by the PCMC chip are:
•
Intel Pentium CPU and CPU at 66/60/50 MHz (external clock speed).
•
Integrated PCI bridge (asynchronous PCI clock always @ 33 MHz).
•
Host bus frequencies of 50, 60, 66.667 MHz.
•
VGA Shared Memory Architecture (with Direct Memory Access):
Direct Memory Accesses;
Shared Memory Area 1M and 2M.
•
PCI arbiter.
•
Pipelined Address Mode of Pentium CPU.
•
Integrated Second Level (L2) Cache Controller.
•
DRAM Controller, supporting:
EDO DRAM;
32-bit/64-bit mix mode.
•
Two Programmable Non-Cacheable Regions.
•
Option to Disable Local Memory in Non-Cacheable Regions.
•
Shadow RAM in Increments of 16 Kbytes.
•
Supports SMM Mode of CPU.
•
Supports CPU Stop Clock.
•
Supports Break Switch.
Summary of Contents for 520 5/XX
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