82
Communication Method
Device-specific Event Status Registers
This device provides two Event Status Registers for controlling events.
The Event Status Register is an 16-bit register.
When any bit in one of these Event Status Registers enabled by its corresponding Enable Register
is set to “1”, the following happens:
•
For Standard Operation Register: Bit 7 (ESB1) of the Status Byte Register is set to “1”.
•
For Status Query Register: Bit 3 (ESB0) of the Status Byte Register is set to “1”.
Event Status Registers 0 and 1 are cleared in the following situations:
•
When a
*CLS
command is executed
•
When an Event Status Register query is executed
(
:STATus:OPERation:EVENt?
,
:STATus:QUEStionable:EVENt?
)
•
When the power is turned on again
HIOKI SW1001A961-04
Summary of Contents for SW9001
Page 2: ...HIOKI SW1001A961 04...
Page 42: ...38 Channel Delay Function HIOKI SW1001A961 04...
Page 48: ...44 Scan Measurement Example HIOKI SW1001A961 04...
Page 50: ...46 Checking the Device Status HIOKI SW1001A961 04...
Page 52: ...48 Initialization Settings HIOKI SW1001A961 04...
Page 118: ...114 Sample Programs 3 Select FILE Save All HIOKI SW1001A961 04...
Page 160: ...156 Outline Drawings 12 4 Outline Drawings SW1001 Unit mm Tolerance 0 2 HIOKI SW1001A961 04...
Page 161: ...157 Outline Drawings SW1002 Unit mm Tolerance 0 2 12 Appendix HIOKI SW1001A961 04...
Page 162: ...158 Outline Drawings HIOKI SW1001A961 04...
Page 164: ...160 HIOKI SW1001A961 04...
Page 167: ...HIOKI SW1001A961 04...
Page 168: ...HIOKI SW1001A961 04...
Page 169: ...HIOKI SW1001A961 04...