Hioki SW9001, Instruction Manual

Page: 82 / 170

78
Communication Method
Status Byte Register (STB)
During serial polling, the contents of the 8-bit Status Byte Register are sent from the instrument to
the controller.
When any Status Byte Register bit enabled by the Service Request Enable Register has switched
from “0” to “1”, the MSS bit becomes “1”. Consequently, the SRQ bit is set to “1”, and a service
request is dispatched.
The SRQ bit is always synchronous with service requests, and is read and simultaneously cleared
during serial polling. Although the MSS bit is only read by an
*
STB?
query, it is not cleared until a
clear event is initiated by the *
CLS
command.
Bit 7 ESB1
Event Summary (logical sum) bit 1
This is the logical sum of the Standard Operation Register.
Bit 6
SRQ
MSS
Set to “1” when a service request is dispatched.
This is the logical sum of the other bits of the Status Byte Register.
Bit 5 ESB
Standard Event Summary (logical sum) bit
This is logical sum of the Standard Event Status Register.
Bit 4 MAV
Message available
Indicates that a message is present in the output queue.
Bit 3 ESB0
Event Summary (logical sum) bit 0
This is the logical sum of the Status Query Register.
Bit 2 ERR
Error bit
Set to “1” when error information is present.
Reset using
:SYSTem.ERRor?
to output error information.
Bit 1 – Unused
Bit 0 – Unused
Service Request Enable Register (SRER)
Setting a bit of this register to “1” enables the corresponding bit of the Status Byte Register to be
used.
HIOKI SW1001A961-04