GE M
EDICAL
S
YSTEMS
PROPRIETARY TO GE
D
IRECTION
2294854-100, R
EVISION
3
LOGIQ™ 9 P
ROPRIETARY
M
ANUAL
7-38
Section 7-9 - Preferred Test Strategy for Memory
7-9-1-3
Strategy for Testing the Internal Memory Cells
To test the internal memory cells, start at the base address and fill the memory with an alternating
pattern of:
0x55555555
0xAAAAAAAA
0x55555555
...
(masked appropriately)
Read and verify the data. Repeat this, filling the memory with an alternating pattern of:
0xAAAAAAAA
0x55555555
0xAAAAAAAA
…
(masked appropriately)
Read and verify the data.
This test for the memory cells is not exhaustive. However, it does ensure that adjacent cells are not
stuck together and that each cell can take on a "1" or a "0" value.
7-9-1-4
Strategy for Testing for Floating Pins (Registers Only)
Anytime a write-then-read operation is performed on a memory location, such as a register, it is possible
for certain faults (e.g. disconnected pins) to go undetected. This is due to the time it takes for a data line
to settle to its default value (through a pull-up resistor). If the write-then-read turnaround time is fast
enough, and a register pin is not connected to the data line on the circuit board, then the read operation
will only reflect the un-relaxed data line, instead of the register's memory cell at that bit.
To uncover a floating pin fault, perform the following steps:
•
Write all zeros to the register - 0x0000 0000 with no mask.
•
Next, write all ones to a different register on the same data bus - 0xFFFF FFFF (again, no mask).
•
Read the first register, apply the data mask, and verify that the data is all zeros. Any 1's in the read
data imply a floating pin at that bit.
