GE M
EDICAL
S
YSTEMS
PROPRIETARY
TO
GE
D
IRECTION
2294854-100, R
EVISION
3
LOGIQ™ 9 P
ROPRIETARY
M
ANUAL
Chapter 5 Components and Functions (Theory)
5-5
Section 5-3
Front End Processor
The Front End Processor generates the strong bursts transmitted by the probes as ultrasound into the
body. It also receives weak ultrasound echoes from blood cells and body structure, amplifies these
signals and converts them to a digital signal.
5-3-1
Front End Processor Power Supply Board (FEPS, FEPS2, FEPS2.1)
The power supply assembly receives approximately 220VAC from the secondary side of the mains
isolation transformer.
The FEPS assembly supplies DC regulated power to the Front End card rack of the LOGIQ™ 9. The
assembly is configured as a PCB which fits into the right-most slot of the Front End card rack. It
interfaces with the back plane to supply power to the Front End circuit boards.
A general enable signal (
PS_ON
) controls enabling and disabling all FEPS Low Voltage outputs. These
i5VA, -5VA, +5V, 3V3, +12V, and +15V (all except PHVP ‘High Voltage’). An Enable circuit on
the FEPS detects when
PS_ON
becomes valid and holds all outputs off until then.
Figure 5-3 The Front End
XDIF
TD
Board
Sum
Rigel
Equalization
Barrel Shift
Digital Gain
NCO
FIR
TGC Gen
XDIF
Control
Commutator
Control
Temperature
Sensors
Power
Supply
Monitors
Scan Bus
Interface
B Mode Processor
Synthetic
Aperture
Axial Interp
Detector
Vector
Compound
Smoothing
Filter
Rate
Converter
Dynamic
Range
Edge
Enhance
Focal
Zone
Splicer
B Mode
M Mode
Output
M Peak
Hold
Scan Bus
Interface
TD
Control
Bus
40P0
40P1
TxSync
BPCLK
HV
Pwr Sup
Control
I,Q
Grey 2D, M
PCI Cable to BEP
Scan Control Board
Scan
Sequencer
TD Control
TxSync
RxSync
Generator
System
Clock
Generator/
Distributor
PCI-PCI
Bridge
Ring Buffer
I,Q
Capture
Processed
Capture
(B, M)
PCI Bus
Scan Bus
T/R Switch
Probe
Port
MUX
A/D
Pulser
RFAmp
PreAmp
TGC
Video
Capture
Top Plane
Front End
Power Supply
240
VAC
+5 V
+3.3 V
+5 V analog
-5 V analog
PS ON
Internal I/O
+12 V
+120 V
I,Q
I2C Master
Scan Bus
PCI Bus