Fujitsu FR Family FR60 Lite, User Manual

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Chapter 26 DMA Controller
3.DMA Controller (DMAC) Operation
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Transfer Count Control
Set the transfer count value in the transfer count register (DTC of DMACA).
The register value is stored in the temporary storage buffer when the transfer starts and is decremented by the
transfer counter. When the counter value becomes 0, end of transfer end for the specified count is detected, and
the transfer on the channel is stopped or waiting for a restart request starts (when reload is specified).
The following are some features of the group of transfer count registers:
• Each register has 16-bit length.
• All registers have a dedicated reload register.
• If transfer is activated when the register value is 0, transfer is performed 65536 times.
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Reload Operation
• The reload operation can be used only if reloading is enabled in a register that allows reloading.
• When transfer is activated, the initial value of the count register is saved in the reload register.
• If the transfer counter counts down to 0, end of transfer is reported and the initial value is read from the reload
register and written to the count register.
3.7 CPU Control
When a DMA transfer request is accepted, DMA issues a transfer request to the bus controller.
The bus controller passes the right to use the internal bus to DMA at a break in bus operation
and DMA transfer starts.
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DMA Transfer and Interrupts
• During DMA transfer, interrupts are generally not accepted until the transfer ends.
• If a DMA transfer request occurs during interrupt processing, the transfer request is accepted and interrupt
processing is stopped until the transfer is completed.
• If, as an exception, an NMI request or an interrupt request with a higher level than the hold suppress level set
by the interrupt controller occurs, DMAC temporarily cancels the transfer request via the bus controller at a
transfer unit boundary (one block) to temporarily stop the transfer until the interrupt request is cleared. In the
meantime, the transfer request is retained internally. After the interrupt request is cleared, DMAC reissues a
transfer request to the bus controller to acquire the right to use the bus and then restarts DMA transfer.
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Suppressing DMA
When an interrupt source with a higher priority occurs during DMA transfer, an FR family device interrupts the
DMA transfer and branches to the relevant interrupt routine. This feature is valid as long as there are any interrupt
requests. When all interrupt sources are cleared, the suppression feature no longer works and the DMA transfer
is restarted by the interrupt processing routine. Thus, if you want to suppress restart of DMA transfer after
clearing interrupt sources in the interrupt source processing routine at a level that interrupts DMA transfer, use
the DMA suppress function. The DMA suppress function can be activated by writing any value other than 0 to the
DMAH[3:0] bits of the DMA all-channel control register and can be stopped by writing 0 to these bits.
This function is mainly used in the interrupt processing routines. Before the interrupt sources in an interrupt
processing routine are cleared, the DMA suppress register is incremented by 1. If this is done, then no DMA
transfer is performed. After interrupt processing, decrement the DMAH[3:0] bits by 1 before returning. If multiple
interrupts have occurred, DMA transfer continues to be suppressed since the DMAH[3:0] bits are not 0 yet. If a
single interrupt has occurred, the DMAH[3:0] bits become 0. DMA requests are then enabled immediately.