Fujitsu FR Family FR60 Lite, User Manual

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Chapter 31 External Bus
2.External Bus Interface Registers
[Bit 6] PSUS (Prefetch suspend)
This bit controls temporary stopping of prefetch to all areas.
If 1 is set, no new prefetch operation is performed before 0 is written. Since during this time the contents of the
prefetch buffer are not deleted unless a prefetch buffer occurs, clear the prefetch buffer using the PCLR bit
function (bit 5) before restarting prefetch.
[Bit 5] PCLR (Prefetch buffer clear)
This bit completely clears the prefetch buffer.
If 1 is written, the prefetch buffer is cleared completely. When clearing is completed, the bit value automatically
returns to 0. Interrupt (set to 1) the prefetch by the PSUS bit (bit 6) and then clear the buffer (It is also possible to
write 11
B
to both the PSUS and PCLR bits).
[Bit 4-2] Reserved
This bit is reserved. Be sure to set it to 0.
[Bits 1,0] RDW1,0 (Reduce Wait cycle)
These bits instruct all chip select areas and fly-by I/O channels to reduce only the number of auto-wait cycles
in the auto-access cycle wait settings uniformly while the AWR register settings are retained unchanged. The
settings for idle cycles, recovery cycles, setup, and hold cycles are not affected.
Table 2-25 "Settings for Wait
Cycle Reduction" lists the settings for the wait cycle reduction for combinations of these bits.
The purpose of this function is to prevent an excessive access cycle wait during operation on a low-speed clock
(for example, when the base clock is switched to low speed or the frequency division ratio setting of the external
bus clock is large).
To reset the wait cycle in these cases, each of the AWRs must usually be rewritten one at a time. However,
when the RDW1/0 bit function is used, the access cycle wait is reduced for all of the AWRs in a single operation
while all of the other high-speed clock settings in each register are retained.
Before returning the clock to high speed, be sure to reset the RDW1/0 bits to 00
B
.
PSUS Prefetch control
0 Enable prefetch
1 Suspend prefetch
PCLR Prefetch buffer control
0 Normal state
1 Clear the prefetch buffer.
Table 2-25 Settings for Wait Cycle Reduction
RDW1 RDW0 Wait cycle reduction
0 0 Normal wait (AWR0-7 settings)
0 1 1/2 (1-bit shift to the right) of the AWR0-7 settings
1 0 1/4 (2-bit shift to the right) of the AWR0-7 settings
1 1 1/8 (3-bit shift to the right) of the AWR0-7 settings