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Fujitsu FR Family FR60 Lite, User Manual

The Fujitsu FR Family FR60 Lite Hardware Manual is your comprehensive guide to understanding and operating this exceptional device. Download this invaluable manual for free at manualshive.com, and unlock the full potential of your FR60 Lite with easy-to-follow instructions and helpful troubleshooting tips.

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Chapter 31  External Bus

2.External Bus Interface Registers

[Bits 2] W02 (Address -> CSn Delay)

The address -> CSn delay setting is made when a certain type of setup is required for the address when CSn
falls or CSn edges are needed for successive accesses to the same chip select area.

Set the address and set the delay from AS output to CS0-CS7 output.

If no delay is selected by setting 0, assertion of CS0-CS7 starts at the same timing that AS is asserted. If, at this
point, successive accesses are made to the same chip select area, assertion of CS0-CS7 without change
between two access operations may continue.

If delay is specified by selecting 1, assertion of CS0-CS7 starts when the external clock memory MCLK output
rises. If, at this point, successive accesses are made to the same chip select area, CS0-CS7 are negated at a
timing between two access operations. If CS delay is selected, one setup cycle is inserted before asserting the
read/write strobe after assertion of the delayed CSn (operation is the same as the CSn ->RD/WE setup setting of
W01).

The address -> CSn delay setting works for DACK signal (basic mode) output to the same area in the same way.
DACK output in basic mode has the same waveforms as those of CS output to the same area.

[Bits 1] W01 (CSn -> RD/WRn Setup Extension Cycle)

The CSn -> RD/WRn setup extension cycle is set to extend the period before the read/write strobe is asserted
after CSn is asserted. At least one setup extension cycle is inserted before the read/write strobe is asserted
after CS is asserted.

If 0 cycle is selected by setting 0, RD/WR0-WR3/WRn are output at the earliest when external clock MCLK output
rises just after CS is asserted. WR0-WR3/WRn may be delayed one cycle or more depending on the internal bus
state.

If 1 cycle is selected by setting 1, RD/WR0-WR3/WRn are always output 1 cycle or more later.

When successive accesses are made within the same chip select area without negating CSn, a setup extension
cycle is not inserted. If a setup extension cycle for determining the address is required, set the W02 bit and insert
the address -> CSn delay.

Since CSn is negated for each access operation, the setup extension cycle is

enabled.

If the CSn delay set by W02 is inserted, this setup cycle is always enabled regardless of the setting of the W01
bit.

W02

Address -> CSn delay

0

No delay

1

Delay

W01

CSn -> RD/WRn setup delay cycle

0

0 cycle

1

1 cycle

Summary of Contents for FR Family FR60 Lite

Page 1: ...FUJITSU SEMICONDUCTOR CONTROLLER MANUAL FR60 32 BIT MICROCONTROLLER MB91460 Series User s Manual Version 1 00 2006 10 22 PRELIMINARY CM71 xxxxx 1E ...

Page 2: ...FUJITSU LIMITED ...

Page 3: ...FR60 32 BIT MICROCONTROLLER MB91460 Series User s Manual ...

Page 4: ...ein The products described in this document are designed developed and manufactured as contemplated for general use including without limitation ordinary industrial use general office use personal use and household use but are not designed developed and manufactured as contemplated 1 for use accompanying fatal risks or dangers that unless extremely high safety is secured could have a serious effec...

Page 5: ...le 73 4 Package 78 5 Pin Assignment Diagram 79 6 Pin Definitions 80 7 I O Circuit Type 94 8 Pin State Table 96 Chapter 4 CPU Architecture 105 1 Overview 105 2 Features 106 3 CPU 107 4 32 bit 16 bit Bus Converter 107 5 Harvard Princeton Bus Converter 107 6 Instruction Overview 108 7 Data Structure 109 8 Word Alignment 110 9 Addressing 111 Chapter 5 CPU Registers 113 1 General purpose Registers 113 ...

Page 6: ...ansition Diagram 134 Chapter 9 Reset 139 1 Overview 139 2 Features 139 3 Configuration 140 4 Registers 141 5 INIT Pin Input INIT Settings Initialization Reset 146 6 Watchdog Reset INIT Settings Initialization Reset 148 7 Software Reset RST Operation Initialization Reset 149 8 Reset Operation Modes 150 9 MCU Operation Mode 151 10 Caution 152 Chapter 10 Standby 155 1 Overview 155 2 Features 155 3 Co...

Page 7: ...ution 205 Chapter 14 PLL Interface 207 1 Overview 207 2 Features 207 3 Frequency calculation 207 4 Registers 208 5 Recommended Settings 212 6 Clock Auto Gear Up Down 213 7 Caution 215 Chapter 15 CAN Clock Prescaler 217 1 Overview 217 2 Features 217 3 Registers 218 Chapter 16 Clock Supervisor 221 1 Overview Clock Supervisor 221 2 Clock Supervisor Register 222 3 Block Diagram Clock Supervisor 224 4 ...

Page 8: ...3 2 Features 273 3 Configuration 274 4 Register 275 5 Operation 278 6 Setting 280 7 Q A 281 8 Caution 282 Chapter 21 Hardware Watchdog Timer 283 1 Overview 283 2 Configuration 284 3 Register 285 4 Functions 287 5 Caution 288 Chapter 22 Main Oscillation Stabilisation Timer 289 1 Overview 289 2 Features 289 3 Configuration 290 4 Register 291 5 Operation 292 6 Setting 294 7 Q A 295 8 Caution 297 Chap...

Page 9: ... Registers 325 5 Operation 327 6 Setting 328 7 Q A 328 8 Caution 331 Chapter 26 DMA Controller 333 1 Overview of the DMA Controller DMAC 333 2 DMA Controller DMAC Registers 335 3 DMA Controller DMAC Operation 354 4 Operation Flowcharts 373 5 Data Bus 376 6 DMA External Interface 379 Chapter 27 Delayed Interrupt 383 1 Overview 383 2 Features 383 3 Configuration 383 4 Register 384 5 Operation 384 6 ...

Page 10: ...Access 543 5 Operation of the Ordinary bus interface 562 6 Burst Access Operation 574 7 Address data Multiplex Interface 576 8 Prefetch Operation 579 9 SDRAM FCRAM Interface Operation 582 10 DMA Access Operation 592 11 Bus Arbitration 608 12 Procedure for Setting a Register 610 13 Notes on Using the External Bus Interface 611 Chapter 32 USART LIN FIFO 613 1 Overview 613 2 USART Configuration 616 3...

Page 11: ...ut Capture 747 1 Overview 747 2 Features 747 3 Configuration 748 4 Register 749 5 Operation 752 6 Settings 754 7 Q A 755 8 Caution 758 Chapter 37 Output Compare 759 1 Overview 759 2 Features 759 3 Configuration Diagram 760 4 Registers 761 5 Operation 765 6 Settings 767 7 Q A 768 8 Caution 773 Chapter 38 Reload Timer 775 1 Overview 775 2 Features 775 3 Configuration 776 4 Registers 778 5 Operation ...

Page 12: ...on 836 4 Register 840 5 Operation 848 6 Setting 855 7 Q A 857 8 Caution 862 Chapter 42 Sound Generator 863 1 Overview 863 2 Block Diagram 864 3 Registers 865 Chapter 43 Stepper Motor Controller 871 1 Overview 871 2 Registers 872 3 Operation 881 4 Caution 883 Chapter 44 A D Converter 885 1 Overview of A D Converter 885 2 Block Diagram of A D Converter 886 3 Registers of A D Converter 887 4 Operatio...

Page 13: ... Registers 924 5 Operation 929 6 Setting 934 7 Q A 935 8 Caution 940 Chapter 48 Clock Monitor 941 1 Overview 941 2 Features 941 3 Configuration 942 4 Register 943 5 Operation 945 6 Settings 946 7 Q A 946 8 Caution 947 Chapter 49 Real Time Clock 949 1 Overview 949 2 Features 949 3 Configuration 950 4 Registers 951 5 Operation 956 6 Setting 958 7 Q A 959 8 Caution 961 Chapter 50 Subclock Calibration...

Page 14: ...k for Boot Conditions 983 3 Registers modified by Boot ROM 988 4 Flash Access Mode Switching 989 5 Bootloader Update Strategy 990 Chapter 54 Flash Memory 993 1 Overview 993 2 Features 993 3 Configuration 994 4 Registers 996 5 Access Modes 996 6 Flash Access Mode Switching 997 7 Auto Algorithms 999 8 Caution 1007 Chapter 55 Flash Security 1009 1 Overview 1009 2 Features 1009 3 Flash Security Vector...

Page 15: ...xi ...

Page 16: ...xii ...

Page 17: ...SS of the device from power supply at low impedance Near the device it is preferable to connect about 0 1uF ceramic capacitor as a bypass capacitor between VCC and VSS Crystal oscillator circuit Noise to X0 or X1 pin may cause an error Make a design for printed board to closely allocate X0 X1 crystal oscillator or ceramic oscillator bypass capacitor towards ground and the device It is recommended ...

Page 18: ... if oscillator is disconnected or input is stopped while selecting PLL clock self excited oscillation circuit in the PLL may continue running at self running frequency This self running operation is not covered by guarantee For more specification about operating voltage see the latest data sheet ...

Page 19: ...atasheets of the flash devices for a valid power on and power off sequence on those devices Power on sequence 1 VDD5 VDD35 HVDD5 VDD5R 2 AVCC AVRH V0 V3 Power off sequence 1 AVCC AVRH V0 V3 2 VDD5 VDD35 HVDD5 VDD5R The power supply V3 for LCD must not exceed VDD5 The power on of V3 should be carried out after power on of VDD5R and VDD5 To power on analogue power supply AVCC and analogue signal pow...

Page 20: ...of ORCCR STILM MOV Ri or PS to enable interruption with interruption by user generated the following operation may be generated 4 PS register is updated ahead 5 EIT processing routine interruption by user is carried out 6 After the return from EIT it executes commands above and then PS register is updated to the same value as 1 Watchdog timer function Watchdog timer function equipped with FR60 mon...

Page 21: ...g to registers which include a status flag Writing to a register including a status flag in particular interrupt request flag in order to control the function note that the actual writing to the registers may be delayed This is because of using write buffers on the busses to the resources which accept a write access from CPU immediately but can access the resource registers delayed In this case it...

Page 22: ...utine is repeatedly executed after the stepwise execution of RETI Therefore main routine or low level interruption program will not be executed To avoid this problem do not proceed stepwise execution of RETI command Or upon the time when no debug is needed for relevant interrupt routine proceed the debug by prohibiting relevant interruptions Operand break Do not set the access for area including s...

Page 23: ...RAM bit search module and internal bus I bus D bus F bus and X bus operations Generated from the base clock in the clock generator Peripheral clock CLKP Peripheral clock is the clock which is referred by each peripheral function peripheral functions other than bit search module and CAN connected to R bus and R bus clock control interrupt controller I O port and external interrupt input d operation...

Page 24: ...rd access is not allowed H W Half word access Word access only Byte access is not allowed Reference The following describes address position to access In Word access address becomes multiple of 4 Lowest order 2 bits mandatorily become 00 In Half word access address becomes multiple of 2 Lowest order 1 bit mandatorily becomes 0 In Byte access address will not be changed Therefore for example make R...

Page 25: ...UCRE RLDE UDCC CGSC CGE1 CGE0 Access size Address Bit position Byte 0B0H 2H 07 06 05 04 03 02 01 00 Half word 0B0H 2H 15 14 13 12 11 10 09 08 Word 0B0H 0H 15 14 13 12 11 10 09 08 Bit name D15 D14 D13 D12 D11 D10 D9 D8 Access size Address Bit position Byte 0B0H 3H 07 06 05 04 03 02 01 00 Half word 0B0H 2H 07 06 05 04 03 02 01 00 Word 0B0H 0H 07 06 05 04 03 02 01 00 Bit name D7 D6 D5 D4 D3 D2 D1 D0 ...

Page 26: ...en Example port data register R RM1 W Readable and writable The read value and written value are different Read modify write command reads 1 Example interrupt request flag R WX Read only Read only Writing does not affect the operation R1 W Write only Write only The read value is 1 R0 W Write only Write only The read value is 0 RX W Write only Write only The read value is indeterminate R W0 Reserve...

Page 27: ...ures 2 1 FR60 CPU Core 32 bit RISC load store architecture pipeline 5 stages Maximum operating frequency Core clock 100 MHz device dependent Source oscillation 4 MHz multiplied by 25 PLL clock multiplier method General purpose registers 16 x 32 bits 16 bit fixed length instruction Base instruction 32 bit linear address space 4 Gbytes Instructions suitable for embedded application Transfer command ...

Page 28: ...askable interrupt pins for Wake Up from STOP mode 2 4 Internal Data RAM Up to 64 kBytes integrated Zero wait state for read write access Referenced as Data RAM or D RAM in this manual 2 5 Internal Instruction Data RAM Up to 64 kBytes integrated Zero wait state for read write access of instructions One wait state for read write access of data Referenced as General Purpose RAM GP RAM or I D RAM in t...

Page 29: ...5 MBit s MOST support MediaLB for controlling an external MOST IC is integrated Digital interface to external MOST controller Frame sync pattern support Scalable data rate for streaming packet control isochronous System broadcast channel for administration Broadcast support for synchronous data USB USB 1 1 compliant up to 12Mbit s USB 2 0 tbd Configurable endpoints Supports control bulk interrupt ...

Page 30: ...arm comparator 2 channels Monitors an external voltage and generates an interrupt in case of a voltage lower or higher than the defined thresholds Status is readable interrupts can be masked separately External interrupt input 16 channels Can be programmed to be edge sensitive or level sensitive Interrupt mask and request pending bits per channel 6 channels combined with CAN RX for wakeup Non mask...

Page 31: ...ble as trigger for PPG 12 13 14 15 External trigger for PPG 0 8 shared External trigger for PPG 1 9 shared External trigger for PPG 2 10 shared External trigger for PPG 3 11 shared External trigger for PPG 4 12 shared External trigger for PPG 5 13 shared External trigger for PPG 6 14 shared External trigger for PPG 7 15 shared Input capture 16 bits x 8 channels Rising edge falling edge or rising f...

Page 32: ...ate for LIN sync field in slave mode LIN USART 5 13 and ICU 5 co operate for LIN sync field in slave mode LIN USART 6 14 and ICU 6 co operate for LIN sync field in slave mode LIN USART 7 15 and ICU 7 co operate for LIN sync field in slave mode CAN 6 channels Supports CAN protocol version 2 0 part A and B Bit rates up to 1 Mbit s Up to 128 message objects Each message object has its own identifier ...

Page 33: ...rom four options for clock peripheral clock or subclock is selectable Driver Built in for internal divided resistors or external divided resistors can be connected to the V0 V3 pins Data memory Built in 16 byte data memory for display Stop mode Enable LCD display in the sub stop mode Blank display Selectable Pin The SEG0 39 of COM0 4 pin usage can be switched between general and specialized purpos...

Page 34: ...ccurate 4 MHz quartz is possible Main oscillation stabilisation timer 23 bit counter for main oscillation stabilisation wait when running in sub clock mode Generates an interrupt when stabilisation time has elapsed Sub oscillation stabilisation timer 15 bit counter for sub oscillation stabilisation wait when running in main clock mode Generates an interrupt when stabilisation time has elapsed Low ...

Page 35: ...M 64 kByte 64 kByte 32 kByte I D bus RAM 64 kByte 64 kByte 32 kByte I bus RAM I Cache 16 kByte 16 kByte 8 kByte Boot ROM BI ROM 4 kByte 4 kByte 4 kByte RTC 1 ch 1 ch 1 ch Free Running Timer 8 ch 8 ch 8 ch ICU 8 ch 8 ch 8 ch OCU 8 ch 8 ch 4 ch Reload Timer 8 ch 8 ch 8 ch PPG 16 bit 16 ch 16 ch 12 ch PFM 16 bit 1 ch 1 ch 1 ch Sound Generator 1 ch 1 ch 1 ch Up Down Counter 8 16 bit 4 ch 8 bit 2 ch 16...

Page 36: ...lator 4 MHz 4 MHz 4 MHz Sub clock oscillator 32 kHz 32 kHz 32 kHz RC Oscillator 100 kHz 100 kHz 2 MHz 100 kHz 2 MHz PLL x 25 x 25 x 25 DSU4 yes yes no EDSU yes yes yes JTAG Boundary Scan no tbd no Supply Voltage 3V 5V tbd 3V 5V Regulator yes tbd yes Power Consumption n a n a 1 W Temperatur Range Ta 0 70 C 0 70 C 40 105 C Package PGA BGA PGA BGA QFP208 Power on to PLL run 20 ms 20 ms 20 ms Flash Do...

Page 37: ...Bus Core Group max 64K words DSU4 Memory Controller FR60 CPU Core EDSU MPU Bit Search CAN DMAC R Unit T Unit I Unit Resources General Purpose Ports External Interrupt max Test Controller Clock Reset Device State Controller SRAM Flash 8MB Queue MB91V460 ICE Interface INT 15 0 Ext Bus Interface GPIOs Resource IOs T Bus X Bus Resource Group Port Group R Bus 64 kByte GP RAM external Trace RAM 1KByte E...

Page 38: ...22 Chapter 2 MB91460 Rev A Rev B Overview 4 Block Diagram ...

Page 39: ... Chapter 3 MB91460 Series Basic Information This chapter describes MB91460 series basic information including Memory and I O map inter rupt vector table pin function list circuit type and pin state table for each device mode 1 Memory Map Figure 1 1 Memory Map ...

Page 40: ...hysical register exists in the position Do not use other data access attributes to access data Address Address offset Register name Block 0 1 2 3 000000H PDRD R W PDR1 R W PDR2 R W PDR3 R W xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx T unit Port data register Read Write attribute R Read W Write Register initial value 0 1 X undefined not implemented Register name First column register is 4n address Second ...

Page 41: ...0 R W XXXXXXXX PDR21 R W XXXXXXXX PDR22 R W XXXXXXXX PDR23 R W XXXXXXXX 000018H PDR24 R W XXXXXXXX PDR25 R W XXXXXXXX PDR26 R W XXXXXXXX PDR27 R W XXXXXXXX 00001CH PDR28 R W XXXXXXXX PDR29 R W XXXXXXXX PDR30 R W XXXXXXXX PDR31 R W XXXXXXXX 000020H PDR32 R W XXXXXXXX PDR33 R W XXXXXXXX PDR34 R W XXXXXXXX PDR35 R W XXXXXXXX 000024H 00002CH reserved 000030H EIRR0 R W 00000000 ENIR0 R W 00000000 ELVR0...

Page 42: ...000 SSR04 R W R 00001000 RDR04 TDR04 R W 00000000 USART LIN 4 with FIFO 000064H ESCR04 R W 00000X00 ECCR04 R W R W 000000XX FSR04 R 00000 FCR04 R W 0001 000 000068H SCR05 R W W 00000000 SMR05 R W W 00000000 SSR05 R W R 00001000 RDR05 TDR05 R W 00000000 USART LIN 5 with FIFO 00006CH ESCR05 R W 00000X00 ECCR05 R W R W 000000XX FSR05 R 00000 FCR05 R W 0001 000 000070H SCR06 R W W 00000000 SMR06 R W W...

Page 43: ...XXXXXXX PWC11 R W XX XXXXXXXX Stepper Motor 1 00009CH res res PWS21 R W 0000000 PWS11 R W 000000 0000A0H PWC22 R W XX XXXXXXXX PWC12 R W XX XXXXXXXX Stepper Motor 2 0000A4H res res PWS22 R W 0000000 PWS12 R W 000000 0000A8H PWC23 R W XX XXXXXXXX PWC13 R W XX XXXXXXXX Stepper Motor 3 0000ACH res res PWS23 R W 0000000 PWS13 R W 000000 0000B0H PWC24 R W XX XXXXXXXX PWC14 R W XX XXXXXXXX Stepper Motor...

Page 44: ...F0H VRAM04 R W XXXXXXXX VRAM05 R W XXXXXXXX VRAM06 R W XXXXXXXX VRAM07 R W XXXXXXXX 0000F4H VRAM08 R W XXXXXXXX VRAM09 R W XXXXXXXX VRAM10 R W XXXXXXXX VRAM11 R W XXXXXXXX 0000F8H VRAM12 R W XXXXXXXX VRAM13 R W XXXXXXXX VRAM14 R W XXXXXXXX VRAM15 R W XXXXXXXX 0000FCH VRAM16 R W XXXXXXXX VRAM17 R W XXXXXXXX VRAM18 R W XXXXXXXX VRAM19 R W XXXXXXXX 000100H GCN10 R W 00110010 00010000 res GCN20 R W 00...

Page 45: ...11111 PCSR06 W XXXXXXXX XXXXXXXX PPG 6 000144H PDUT06 W XXXXXXXX XXXXXXXX PCNH06 R W 0000000 PCNL06 R W 000000 0 000148H PTMR07 R 11111111 11111111 PCSR07 W XXXXXXXX XXXXXXXX PPG 7 00014CH PDUT07 W XXXXXXXX XXXXXXXX PCNH07 R W 0000000 PCNL07 R W 000000 0 000150H PTMR08 R 11111111 11111111 PCSR08 W XXXXXXXX XXXXXXXX PPG 8 000154H PDUT08 W XXXXXXXX XXXXXXXX PCNH08 R W 0000000 PCNL08 R W 000000 0 000...

Page 46: ...are 0 3 000190H OCCP0 R W XXXXXXXX XXXXXXXX OCCP1 R W XXXXXXXX XXXXXXXX 000194H OCCP2 R W XXXXXXXX XXXXXXXX OCCP3 R W XXXXXXXX XXXXXXXX 000198H SGCRH R W 0000 00 SGCRL R W 0 000 SGFR R W R XXXXXXXX XXXXXXXX Sound Generator 00019CH SGAR R W 00000000 res SGTR R W XXXXXXXX SGDR R W XXXXXXXX 0001A0H ADERH R W 00000000 00000000 ADERL R W 00000000 00000000 A D Converter 0001A4 ADCS1 R W 00000000 ADCS0 R...

Page 47: ...X XXXXXXXX Reload Timer 4 PPG 8 9 0001D4H reserved TMCSRH4 R W 00000 TMCSRL4 R W 0 000000 0001D8H TMRLR5 W XXXXXXXX XXXXXXXX TMR5 R XXXXXXXX XXXXXXXX Reload Timer 5 PPG 10 11 0001DCH reserved TMCSRH5 R W 00000 TMCSRL5 R W 0 000000 0001E0H TMRLR6 W XXXXXXXX XXXXXXXX TMR6 R XXXXXXXX XXXXXXXX Reload Timer 6 PPG 12 13 0001E4H reserved TMCSRH6 R W 00000 TMCSRL6 R W 0 000000 0001E8H TMRLR7 W XXXXXXXX XX...

Page 48: ... R W 00000000 00000000 XXXXXXXX XXXXXXXX 000210H DMACA2 R W 00000000 0000XXXX XXXXXXXX XXXXXXXX 000214H DMACB2 R W 00000000 00000000 XXXXXXXX XXXXXXXX 000218H DMACA3 R W 00000000 0000XXXX XXXXXXXX XXXXXXXX 00021CH DMACB3 R W 00000000 00000000 XXXXXXXX XXXXXXXX 000220H DMACA4 R W 00000000 0000XXXX XXXXXXXX XXXXXXXX 000224H DMACB4 R W 00000000 00000000 XXXXXXXX XXXXXXXX 000228H 00023CH reserved 0002...

Page 49: ... 00000000 SSR10 R W R 00001000 RDR10 TDR10 R W 00000000 USART LIN 10 000294H ESCR10 R W 00000X00 ECCR10 R W R W 000000XX res 000298H SCR11 R W W 00000000 SMR11 R W W 00000000 SSR11 R W R 00001000 RDR11 TDR11 R W 00000000 USART LIN 11 00029CH ESCR11 R W 00000X00 ECCR11 R W R W 000000XX res 0002A0H SCR12 R W W 00000000 SMR12 R W W 00000000 SSR12 R W R 00001000 RDR12 TDR12 R W 00000000 USART LIN 12 0...

Page 50: ...00 BGR111 R W 00000000 BGR011 R W 00000000 0002C8H BGR112 R W 00000000 BGR012 R W 00000000 BGR113 R W 00000000 BGR013 R W 00000000 0002CCH BGR114 R W 00000000 BGR014 R W 00000000 BGR15 R W 00000000 BGR015 R W 00000000 0002D0H res ICS45 R W 00000000 res ICS67 R W 00000000 Input Capture 4 7 0002D4H IPCP4 R XXXXXXXX XXXXXXXX IPCP5 R XXXXXXXX XXXXXXXX 0002D8H IPCP6 R XXXXXXXX XXXXXXXX IPCP7 R XXXXXXXX...

Page 51: ... R W 00000000 res UDCS1 R W 00000000 00030CH reserved 000310H UDRC3 W 00000000 UDRC2 W 00000000 UDCR3 R 00000000 UDCR2 R 00000000 Up Down Counter 2 3 000314H UDCCH2 R W 00001000 UDCCL2 R W 00000000 res UDCS2 R W 00000000 000318H UDCCH3 R W 00001000 UDCCL3 R W 00000000 res UDCS3 R W 00000000 00031CH reserved 000320H GCN13 R W 00110010 00010000 res GCN23 R W 0000 PPG Control 12 15 000324H 00032CH re...

Page 52: ...1 R W XX XXXXXXXX 000368H IBCR2 R W 00000000 IBSR2 R 00000000 ITBAH2 R W 00 ITBAL2 R W 00000000 I2C 2 00036CH ITMKH2 R W 00 11 ITMKL2 R W 11111111 ISMK2 R W 01111111 ISBA2 R W 0000000 000370H res IDAR2 R W 00000000 ICCR2 R W 0011111 res 000374H IBCR3 R W 00000000 IBSR3 R 00000000 ITBAH3 R W 00 ITBAL3 R W 00000000 I2C 3 000378H ITMKH3 R W 00 11 ITMKL3 R W 11111111 ISMK3 R W 01111111 ISBA3 R W 00000...

Page 53: ...00 I Cache 0003E8H 0003ECH reserved 0003F0H BSD0 W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Bit Search Module 0003F4H BSD1 R W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F8H BSDC W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003FCH BSRR R XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000400H 00043CH reserved Address Register Block 0 1 2 3 ...

Page 54: ...W 11111 000460H ICR32 R W 11111 ICR33 R W 11111 ICR34 R W 11111 ICR35 R W 11111 000464H ICR36 R W 11111 ICR37 R W 11111 ICR38 R W 11111 ICR39 R W 11111 000468H ICR40 R W 11111 ICR41 R W 11111 ICR42 R W 11111 ICR43 R W 11111 00046CH ICR44 R W 11111 ICR45 R W 11111 ICR46 R W 11111 ICR47 R W 11111 000470H ICR48 R W 11111 ICR49 R W 11111 ICR50 R W 11111 ICR51 R W 11111 000474H ICR52 R W 11111 ICR53 R ...

Page 55: ...0011100 CSCFG R W 0X000000 CMCFG R W 00000000 Clock Supervisor Selector Monitor 0004B0H CUCR R W 0 00 CUTD R W 10000000 00000000 Calibration Unit of Sub Oscillation 0004B4H CUTR1 R 00000000 CUTR2 R 00000000 00000000 0004B8H CMPR R W 000010 11111101 res CMCR R W 001 00 Clock Modulation 0004BCH CMT1 R W 00000000 1 0000 CMT2 R W 000000 000000 0004C0H CANPRE R W 0 0000 CANCKD R W 000000 res res CAN Cl...

Page 56: ...0R R W 0 res EISSRH R W 00000000 EISSRL R W 00000000 340 Compati bility Mode do not use 0004D4H SHDE R W 0 res EXTE R W 00000000 EXTF R W 00000000 Supply Shut Down Mode 0004D8H EXTLV R W 00000000 00000000 res res 0004DCH 00063CH reserved Address Register Block 0 1 2 3 ...

Page 57: ... XXXXXXXX ACR7 R W XXXXXXXX XXXXXXXX 000660H AWR0 R W 01111111 11111 11 AWR1 R W XXXXXXXX XXXXXXXX 000664H AWR2 R W XXXXXXXX XXXXXXXX AWR3 R W XXXXXXXX XXXXXXXX 000668H AWR4 R W XXXXXXXX XXXXXXXX AWR5 R W XXXXXXXX XXXXXXXX 00066CH AWR6 R W XXXXXXXX XXXXXXXX AWR7 R W XXXXXXXX XXXXXXXX 000670H MCRA R W XXXXXXXX MCRB R W XXXXXXXX reserved 000674H reserved 000678H IOWR0 R W XXXXXXXX IOWR1 R W XXXXXXXX...

Page 58: ...7 R XXXXXXXX 000D08H PDRD08 R XXXXXXXX PDRD09 R XXXXXXXX PDRD10 R XXXXXXXX PDRD11 R XXXXXXXX 000D0CH PDRD12 R XXXXXXXX PDRD13 R XXXXXXXX PDRD14 R XXXXXXXX PDRD15 R XXXXXXXX 000D10H PDRD16 R XXXXXXXX PDRD17 R XXXXXXXX PDRD18 R XXXXXXXX PDRD19 R XXXXXXXX 000D14H PDRD20 R XXXXXXXX PDRD21 R XXXXXXXX PDRD22 R XXXXXXXX PDRD23 R XXXXXXXX 000D18H PDRD24 R XXXXXXXX PDRD25 R XXXXXXXX PDRD26 R XXXXXXXX PDRD2...

Page 59: ...DR31 R W 00000000 000D60H DDR32 R W 00000000 DDR33 R W 00000000 DDR34 R W 00000000 DDR35 R W 00000000 000D64H 000D7CH reserved 000D80H PFR00 R W 11111111 PFR01 R W 11111111 PFR02 R W 11111111 PFR03 R W 11111111 R bus Port Function Register 000D84H PFR04 R W 11111111 PFR05 R W 11111111 PFR06 R W 11111111 PFR07 R W 11111111 000D88H PFR08 R W 11111111 PFR09 R W 11111111 PFR10 R W 11111111 PFR11 R W 0...

Page 60: ...00DCCH EPFR12 R W 00000000 EPFR13 R W 00000000 EPFR14 R W 00000000 EPFR15 R W 00000000 000DD0H EPFR16 R W 00000000 EPFR17 R W 00000000 EPFR18 R W 00000000 EPFR19 R W 00000000 000DD4H EPFR20 R W 00000000 EPFR21 R W 00000000 EPFR22 R W 00000000 EPFR23 R W 00000000 000DD8H EPFR24 R W 00000000 EPFR25 R W 00000000 EPFR26 R W 00000000 EPFR27 R W 00000000 000DDCH EPFR28 R W 00000000 EPFR29 R W 00000000 E...

Page 61: ... R W 00000000 000E20H PODR32 R W 00000000 PODR33 R W 00000000 PODR34 R W 00000000 PODR35 R W 00000000 000E24H 000E3CH reserved 000E40H PILR00 R W 00000000 PILR01 R W 00000000 PILR02 R W 00000000 PILR03 R W 00000000 R bus Port Input Level Select Register 000E44H PILR04 R W 00000000 PILR05 R W 00000000 PILR06 R W 00000000 PILR07 R W 00000000 000E48H PILR08 R W 00000000 PILR09 R W 00000000 PILR10 R W...

Page 62: ...0E8CH EPILR12 R W 00000000 EPILR13 R W 00000000 EPILR14 R W 00000000 EPILR15 R W 00000000 000E90H EPILR16 R W 00000000 EPILR17 R W 00000000 EPILR18 R W 00000000 EPILR19 R W 00000000 000E94H EPILR20 R W 00000000 EPILR21 R W 00000000 EPILR22 R W 00000000 EPILR23 R W 00000000 000E98H EPILR24 R W 00000000 EPILR25 R W 00000000 EPILR26 R W 00000000 EPILR27 R W 00000000 000E9CH EPILR28 R W 00000000 EPILR...

Page 63: ...R W 00000000 000EE0H PPER32 R W 00000000 PPER33 R W 00000000 PPER34 R W 00000000 PPER35 R W 00000000 000EE4H 000EFCH reserved 000F00H PPCR00 R W 11111111 PPCR01 R W 11111111 PPCR02 R W 11111111 PPCR03 R W 11111111 R bus Port Pull Up Down Control Register 000F04H PPCR04 R W 11111111 PPCR05 R W 11111111 PPCR06 R W 11111111 PPCR07 R W 11111111 000F08H PPCR08 R W 11111111 PPCR09 R W 11111111 PPCR10 R ...

Page 64: ...18H DMASA3 R W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00101CH DMADA3 R W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001020H DMASA4 R W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001024H DMADA4 R W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001028H 006FFCH reserved 007000H FMCS R W 01101000 res FCHCR R W 00 10000011 Flash Memory I Cache Control Register 007004H FMWT R W 11111111 11111111 res FMPS R W 000 007008H FMAC R 00...

Page 65: ...0 CBSYNC0 2 00C010H IF1CREQ0 R W 00000000 00000001 IF1CMSK0 R W 00000000 00000000 CAN 0 IF 1 Register 00C014H IF1MSK20 R W 11111111 11111111 IF1MSK10 R W 11111111 11111111 00C018H IF1ARB20 R W 00000000 00000000 IF1ARB10 R W 00000000 00000000 00C01CH IF1MCTR0 R W 00000000 00000000 res 00C020H IF1DTA10 R W 00000000 00000000 IF1DTA20 R W 00000000 00000000 00C024H IF1DTB10 R W 00000000 00000000 IF1DTB...

Page 66: ...0 00000000 IF2ARB10 R W 00000000 00000000 00C04CH IF2MCTR0 R W 00000000 00000000 res 00C050H IF2DTA10 R W 00000000 00000000 IF2DTA20 R W 00000000 00000000 00C054H IF2DTB10 R W 00000000 00000000 IF2DTB20 R W 00000000 00000000 00C058H 00C05CH reserved 00C060H IF2DTA20 R W 00000000 00000000 IF2DTA10 R W 00000000 00000000 00C064H IF2DTB20 R W 00000000 00000000 IF2DTB10 R W 00000000 00000000 00C068H 00...

Page 67: ...0 00000000 NEWDT50 R 00000000 00000000 00C09CH NEWDT80 R 00000000 00000000 NEWDT70 R 00000000 00000000 00C0A0H INTPND20 R 00000000 00000000 INTPND10 R 00000000 00000000 00C0A4H INTPND40 R 00000000 00000000 INTPND30 R 00000000 00000000 00C0A8H INTPND60 R 00000000 00000000 INTPND50 R 00000000 00000000 00C0ACH INTPND80 R 00000000 00000000 INTPND70 R 00000000 00000000 00C0B0H MSGVAL20 R 00000000 00000...

Page 68: ...000 00000000 CAN 1 IF 1 Register 00C114H IF1MSK21 R W 11111111 11111111 IF1MSK11 R W 11111111 11111111 00C118H IF1ARB21 R W 00000000 00000000 IF1ARB11 R W 00000000 00000000 00C11CH IF1MCTR1 R W 00000000 00000000 res 00C120H IF1DTA11 R W 00000000 00000000 IF1DTA21 R W 00000000 00000000 00C124H IF1DTB11 R W 00000000 00000000 IF1DTB21 R W 00000000 00000000 00C128H 00C12CH reserved 00C130H IF1DTA21 R ...

Page 69: ...0 00000000 IF2ARB11 R W 00000000 00000000 00C14CH IF2MCTR1 R W 00000000 00000000 res 00C150H IF2DTA11 R W 00000000 00000000 IF2DTA21 R W 00000000 00000000 00C154H IF2DTB11 R W 00000000 00000000 IF2DTB21 R W 00000000 00000000 00C158H 00C15CH reserved 00C160H IF2DTA21 R W 00000000 00000000 IF2DTA11 R W 00000000 00000000 00C164H IF2DTB21 R W 00000000 00000000 IF2DTB11 R W 00000000 00000000 00C168H 00...

Page 70: ...0 00000000 NEWDT51 R 00000000 00000000 00C19CH NEWDT81 R 00000000 00000000 NEWDT71 R 00000000 00000000 00C1A0H INTPND21 R 00000000 00000000 INTPND11 R 00000000 00000000 00C1A4H INTPND41 R 00000000 00000000 INTPND31 R 00000000 00000000 00C1A8H INTPND61 R 00000000 00000000 INTPND51 R 00000000 00000000 00C1ACH INTPND81 R 00000000 00000000 INTPND71 R 00000000 00000000 00C1B0H MSGVAL21 R 00000000 00000...

Page 71: ...000 00000000 CAN 2 IF 1 Register 00C214H IF1MSK22 R W 11111111 11111111 IF1MSK12 R W 11111111 11111111 00C218H IF1ARB22 R W 00000000 00000000 IF1ARB12 R W 00000000 00000000 00C21CH IF1MCTR2 R W 00000000 00000000 res 00C220H IF1DTA12 R W 00000000 00000000 IF1DTA22 R W 00000000 00000000 00C224H IF1DTB12 R W 00000000 00000000 IF1DTB22 R W 00000000 00000000 00C228H 00C22CH reserved 00C230H IF1DTA22 R ...

Page 72: ...0 00000000 IF2ARB12 R W 00000000 00000000 00C24CH IF2MCTR2 R W 00000000 00000000 res 00C250H IF2DTA12 R W 00000000 00000000 IF2DTA22 R W 00000000 00000000 00C254H IF2DTB12 R W 00000000 00000000 IF2DTB22 R W 00000000 00000000 00C258H 00C25CH reserved 00C260H IF2DTA22 R W 00000000 00000000 IF2DTA12 R W 00000000 00000000 00C264H IF2DTB22 R W 00000000 00000000 IF2DTB12 R W 00000000 00000000 00C268H 00...

Page 73: ...0 00000000 NEWDT52 R 00000000 00000000 00C29CH NEWDT82 R 00000000 00000000 NEWDT72 R 00000000 00000000 00C2A0H INTPND22 R 00000000 00000000 INTPND12 R 00000000 00000000 00C2A4H INTPND42 R 00000000 00000000 INTPND32 R 00000000 00000000 00C2A8H INTPND62 R 00000000 00000000 INTPND52 R 00000000 00000000 00C2ACH INTPND82 R 00000000 00000000 INTPND72 R 00000000 00000000 00C2B0H MSGVAL22 R 00000000 00000...

Page 74: ...000 00000000 CAN 3 IF 1 Register 00C314H IF1MSK23 R W 11111111 11111111 IF1MSK13 R W 11111111 11111111 00C318H IF1ARB23 R W 00000000 00000000 IF1ARB13 R W 00000000 00000000 00C31CH IF1MCTR3 R W 00000000 00000000 res 00C320H IF1DTA13 R W 00000000 00000000 IF1DTA23 R W 00000000 00000000 00C324H IF1DTB13 R W 00000000 00000000 IF1DTB23 R W 00000000 00000000 00C328H 00C32CH reserved 00C330H IF1DTA23 R ...

Page 75: ...0 00000000 IF2ARB13 R W 00000000 00000000 00C34CH IF2MCTR3 R W 00000000 00000000 res 00C350H IF2DTA13 R W 00000000 00000000 IF2DTA23 R W 00000000 00000000 00C354H IF2DTB13 R W 00000000 00000000 IF2DTB23 R W 00000000 00000000 00C358H 00C35CH reserved 00C360H IF2DTA23 R W 00000000 00000000 IF2DTA13 R W 00000000 00000000 00C364H IF2DTB23 R W 00000000 00000000 IF2DTB13 R W 00000000 00000000 00C368H 00...

Page 76: ...0 00000000 NEWDT53 R 00000000 00000000 00C39CH NEWDT83 R 00000000 00000000 NEWDT73 R 00000000 00000000 00C3A0H INTPND23 R 00000000 00000000 INTPND13 R 00000000 00000000 00C3A4H INTPND43 R 00000000 00000000 INTPND33 R 00000000 00000000 00C3A8H INTPND63 R 00000000 00000000 INTPND53 R 00000000 00000000 00C3ACH INTPND83 R 00000000 00000000 INTPND73 R 00000000 00000000 00C3B0H MSGVAL23 R 00000000 00000...

Page 77: ...000 00000000 CAN 4 IF 1 Register 00C414H IF1MSK24 R W 11111111 11111111 IF1MSK14 R W 11111111 11111111 00C418H IF1ARB24 R W 00000000 00000000 IF1ARB14 R W 00000000 00000000 00C41CH IF1MCTR4 R W 00000000 00000000 res 00C420H IF1DTA14 R W 00000000 00000000 IF1DTA24 R W 00000000 00000000 00C424H IF1DTB14 R W 00000000 00000000 IF1DTB24 R W 00000000 00000000 00C428H 00C42CH reserved 00C430H IF1DTA24 R ...

Page 78: ...0 00000000 IF2ARB14 R W 00000000 00000000 00C44CH IF2MCTR4 R W 00000000 00000000 res 00C450H IF2DTA14 R W 00000000 00000000 IF2DTA24 R W 00000000 00000000 00C454H IF2DTB14 R W 00000000 00000000 IF2DTB24 R W 00000000 00000000 00C458H 00C45CH reserved 00C460H IF2DTA24 R W 00000000 00000000 IF2DTA14 R W 00000000 00000000 00C464H IF2DTB24 R W 00000000 00000000 IF2DTB14 R W 00000000 00000000 00C468H 00...

Page 79: ...0 00000000 NEWDT54 R 00000000 00000000 00C49CH NEWDT84 R 00000000 00000000 NEWDT74 R 00000000 00000000 00C4A0H INTPND24 R 00000000 00000000 INTPND14 R 00000000 00000000 00C4A4H INTPND44 R 00000000 00000000 INTPND34 R 00000000 00000000 00C4A8H INTPND64 R 00000000 00000000 INTPND54 R 00000000 00000000 00C4ACH INTPND84 R 00000000 00000000 INTPND74 R 00000000 00000000 00C4B0H MSGVAL24 R 00000000 00000...

Page 80: ...000 00000000 CAN 5 IF 1 Register 00C514H IF1MSK25 R W 11111111 11111111 IF1MSK15 R W 11111111 11111111 00C518H IF1ARB25 R W 00000000 00000000 IF1ARB15 R W 00000000 00000000 00C51CH IF1MCTR5 R W 00000000 00000000 res 00C520H IF1DTA15 R W 00000000 00000000 IF1DTA25 R W 00000000 00000000 00C524H IF1DTB15 R W 00000000 00000000 IF1DTB25 R W 00000000 00000000 00C528H 00C52CH reserved 00C530H IF1DTA25 R ...

Page 81: ...0 00000000 IF2ARB15 R W 00000000 00000000 00C54CH IF2MCTR5 R W 00000000 00000000 res 00C550H IF2DTA15 R W 00000000 00000000 IF2DTA25 R W 00000000 00000000 00C554H IF2DTB15 R W 00000000 00000000 IF2DTB25 R W 00000000 00000000 00C558H 00C55CH reserved 00C560H IF2DTA25 R W 00000000 00000000 IF2DTA15 R W 00000000 00000000 00C564H IF2DTB25 R W 00000000 00000000 IF2DTB15 R W 00000000 00000000 00C568H 00...

Page 82: ...0 00000000 NEWDT55 R 00000000 00000000 00C59CH NEWDT85 R 00000000 00000000 NEWDT75 R 00000000 00000000 00C5A0H INTPND25 R 00000000 00000000 INTPND15 R 00000000 00000000 00C5A4H INTPND45 R 00000000 00000000 INTPND35 R 00000000 00000000 00C5A8H INTPND65 R 00000000 00000000 INTPND55 R 00000000 00000000 00C5ACH INTPND85 R 00000000 00000000 INTPND75 R 00000000 00000000 00C5B0H MSGVAL25 R 00000000 00000...

Page 83: ...00000 00000000 00000000 00000000 00F014H 00F01CH reserved 00F020H BCR0 R W 00000000 00000000 00000000 00F024H BCR1 R W 00000000 00000000 00000000 00F028H BCR2 R W 00000000 00000000 00000000 00F02CH BCR3 R W 00000000 00000000 00000000 00F030H BCR4 R W 00000000 00000000 00000000 00F034H BCR5 R W 00000000 00000000 00000000 00F038H BCR6 R W 00000000 00000000 00000000 00F03CH BCR7 R W 00000000 00000000...

Page 84: ...XXXXXXXX 00F098H BAD6 R W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F09CH BAD7 R W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0A0H BAD8 R W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0A4H BAD9 R W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0A8H BAD10 R W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0ACH BAD11 R W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0B0H BAD12 R W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0B4H BAD13 R W...

Page 85: ...F0D8H BAD22 R W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0DCH BAD23 R W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0E0H BAD24 R W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0E4H BAD25 R W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0E8H BAD26 R W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0ECH BAD27 R W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0F0H BAD28 R W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0F4H BAD29 R W XXXXXX...

Page 86: ... 010000H 013FFCH Cache TAG way 1 010000H 0107FCH 2 way set associative I Cache 4kB 014000H 017FFCH Cache TAG way 2 014000H 0147FCH 018000H 01BFFCH Cache RAM way 1 018000H 0187FCH 01C000H 01FFFCH Cache RAM way 2 01C000H 01C7FCH Address Register Block 0 1 2 3 ...

Page 87: ...waitcycle I D RAM 64 kB 040000H 05FFFCH ROMS00 area 128kB 060000H 07FFFCH ROMS01 area 128kB 080000H 09FFFCH ROMS02 area 128kB 0A0000H 0BFFFCH ROMS03 area 128kB 0C0000H 0DFFFCH ROMS04 area 128kB 0E0000H 0FFFF4H ROMS05 area 128kB 0FFFF8H FMV R 06 00 00 00H Fixed Reset Mode Vector 0FFFFCH FRV R 00 00 BF F8H 100000H 13FFFCH ROMS06 area 256kB 140000H 17FFFCH ROMS07 area 256kB 180000H 1BFFFCH ROMS08 are...

Page 88: ...or halfword to this address to synchronize the CPU operation e g the interrupt accep tance of the CPU to a preceding write access to the CANs on D bus e g to an interrupt flag on following addresses 0xC000 0xFFFF 200000H 27FFFCH ROMS10 area 512kB 280000H 2FFFFCH ROMS11 area 512kB 300000H 37FFFCH ROMS12 area 512kB 380000H 3FFFFCH ROMS13 area 512kB 400000H 47FFFCH ROMS14 area 512kB 480000H 4FFFFCH R...

Page 89: ...or fault trap 5 7 07 0x3E0 0x000FFFE0 Co processor error trap 5 8 08 0x3DC 0x000FFFDC INTE instruction 5 9 09 0x3D8 0x000FFFD8 Instruction break exception 5 10 0A 0x3D4 0x000FFFD4 Operand break trap 5 11 0B 0x3D0 0x000FFFD0 Step trace trap 5 12 0C 0x3CC 0x000FFFCC NMI interrupt tool 5 13 0D 0x3C8 0x000FFFC8 Undefined instruction exception 14 0E 0x3C4 0x000FFFC4 NMI request 15 0F FH fixed 0x3C0 0x0...

Page 90: ...ad Timer 5 37 25 0x368 0x000FFF68 37 Reload Timer 6 38 26 ICR11 0x44B 0x364 0x000FFF64 38 Reload Timer 7 39 27 0x360 0x000FFF60 39 Free Run Timer 0 40 28 ICR12 0x44C 0x35C 0x000FFF5C 40 Free Run Timer 1 41 29 0x358 0x000FFF58 41 Free Run Timer 2 42 2A ICR13 0x44D 0x354 0x000FFF54 42 Free Run Timer 3 43 2B 0x350 0x000FFF50 43 Free Run Timer 4 44 2C ICR14 0x44E 0x34C 0x000FFF4C 44 Free Run Timer 5 4...

Page 91: ...000FFEE0 61 USART LIN FIFO 7 RX 72 48 ICR28 0x45C 0x2DC 0x000FFEDC 62 USART LIN FIFO 7 TX 73 49 0x2D8 0x000FFED8 63 I2C 0 I2C 2 74 4A ICR29 0x45D 0x2D4 0x000FFED4 I2C 1 I2C 3 75 4B 0x2D0 0x000FFED0 USART LIN 8 RX 76 4C ICR30 0x45E 0x2CC 0x000FFECC 64 USART LIN 8 TX 77 4D 0x2C8 0x000FFEC8 65 USART LIN 9 RX 78 4E ICR31 0x45F 0x2C4 0x000FFEC4 66 USART LIN 9 TX 79 4F 0x2C0 0x000FFEC0 67 USART LIN 10 R...

Page 92: ...R45 0x46D 0x254 0x000FFE54 94 Output Compare 7 107 6B 0x250 0x000FFE50 95 Sound Generator 108 6C ICR46 0x46E 0x24C 0x000FFE4C Pulse Frequ Modulator 109 6D 0x248 0x000FFE48 System reserved 110 6E ICR47 4 0x46F 0x244 0x000FFE44 System reserved 111 6F 0x240 0x000FFE40 Prog Pulse Gen 0 112 70 ICR48 0x470 0x23C 0x000FFE3C 15 96 Prog Pulse Gen 1 113 71 0x238 0x000FFE38 97 Prog Pulse Gen 2 114 72 ICR49 0...

Page 93: ...n flash devices 8 RN resource number used for DMA operation No number means that this resource interrupt cannot be used to trigger a DMA transfer Prog Pulse Gen 14 126 7E ICR55 0x477 0x204 0x000FFE04 110 Prog Pulse Gen 15 127 7F 0x200 0x000FFE00 111 Up Down Counter 0 128 80 ICR56 0x478 0x1FC 0x000FFDFC Up Down Counter 1 129 81 0x1F8 0x000FFDF8 Up Down Counter 2 130 82 ICR57 0x479 0x1F4 0x000FFDF4 ...

Page 94: ...78 Chapter 3 MB91460 Series Basic Information 4 Package 4 Package BGA 660P M02 package BGA660 03EK MB91V460 Figure 4 1 External Dimension of BGA660 03EK ...

Page 95: ...79 Chapter 3 MB91460 Series Basic Information 5 Pin Assignment Diagram 5 Pin Assignment Diagram MB91V460 BGA660 package Figure 5 1 Pin Assignment Diagram of BGA660 03EK ...

Page 96: ... Stop TTL extbus 4mA AG38 293 245 P02_7 D15 D15 TP04_0 U D CH A TTL Stop TTL extbus 4mA AE37 292 243 P02_6 D14 D14 TP04_0 U D CH A TTL Stop TTL extbus 4mA AE36 289 241 P02_5 D13 D13 TP04_0 U D CH A TTL Stop TTL extbus 4mA AD37 288 240 P02_4 D12 D12 TP04_0 U D CH A TTL Stop TTL extbus 4mA AD36 287 239 P02_3 D11 D11 TP04_0 U D CH A TTL Stop TTL extbus 4mA AC37 286 238 P02_2 D10 D10 TP04_0 U D CH A T...

Page 97: ... TTL Stop TTL extbus 4mA L37 224 184 P07_7 A7 A7 TP04_0 U D CH A TTL Stop TTL extbus 4mA M38 221 182 P07_6 A6 A6 TP04_0 U D CH A TTL Stop TTL extbus 4mA M35 220 181 P07_5 A5 A5 TP04_0 U D CH A TTL Stop TTL extbus 4mA L38 219 180 P07_4 A4 A4 TP04_0 U D CH A TTL Stop TTL extbus 4mA L35 218 179 P07_3 A3 A3 TP04_0 U D CH A TTL Stop TTL extbus 4mA M36 217 178 P07_2 A2 A2 TP04_0 U D CH A TTL Stop TTL ex...

Page 98: ...OP2 TP04_0 U D CH A TTL Stop TTL extbus 4mA B33 159 132 P12_2 DEOTX2 DEOTX2 DEOP2 TP04_0 U D CH A TTL Stop TTL extbus 4mA C32 158 131 P12_1 DACKX2 DACKX2 TP04_0 U D CH A TTL Stop TTL extbus 4mA A34 156 130 P12_0 DREQ2 DREQ2 TP04_0 U D CH A TTL Stop TTL extbus 4mA B32 155 129 P13_7 DEOP1 DEOP1 TP04_0 U D CH A TTL Stop TTL extbus 4mA A33 154 128 P13_6 DEOTX1 DEOTX1 DEOP1 TP04_0 U D CH A TTL Stop TTL...

Page 99: ...U D CH A Stop 4mA A23 98 83 P18_6 SCK7 ZIN3 CK7 TP00_0 U D CH A Stop 4mA C21 97 80 P18_5 SOT7 BIN3 TP00_0 U D CH A Stop 4mA A22 94 79 P18_4 SIN7 AIN3 TP00_0 U D CH A Stop 4mA D21 93 77 P18_3 TP00_0 U D CH A Stop 4mA A21 92 78 P18_2 SCK6 ZIN2 CK6 TP00_0 U D CH A Stop 4mA D20 91 75 P18_1 SOT6 BIN2 TP00_0 U D CH A Stop 4mA B20 90 76 P18_0 SIN6 AIN2 TP00_0 U D CH A Stop 4mA C20 89 73 P19_7 TP00_0 U D ...

Page 100: ...10 38 31 P23_0 RX0 INT8 TP00_0 U D CH A Stop 4mA A9 36 29 P24_7 INT7 SCL3 TP02_0 CH A Stop I2C 3mA D10 35 28 P24_6 INT6 SDA3 TP02_0 CH A Stop I2C 3mA C10 34 26 P24_5 INT5 SCL2 TP02_0 CH A Stop I2C 3mA D9 33 27 P24_4 INT4 SDA2 TP02_0 CH A Stop I2C 3mA C9 32 25 P24_3 INT3 TP00_0 U D CH A Stop 4mA B8 29 24 P24_2 INT2 TP00_0 U D CH A Stop 4mA B7 27 23 P24_1 INT1 TP00_0 U D CH A Stop 4mA A8 26 20 P24_0...

Page 101: ...6 TP03_0 U D CH A Stop AN 4mA B3 3 2 P29_5 AN5 TP03_0 U D CH A Stop AN 4mA C4 2 1 P29_4 AN4 TP03_0 U D CH A Stop AN 4mA C2 690 578 P29_3 AN3 TP03_0 U D CH A Stop AN 4mA D3 689 577 P29_2 AN2 TP03_0 U D CH A Stop AN 4mA J1 653 544 P29_1 AN1 TP03_0 U D CH A Stop AN 4mA L2 650 543 P29_0 AN0 TP03_0 U D CH A Stop AN 4mA K1 651 542 P30_7 V3 TP08_0 CH A Stop LCD V3 4mA M2 648 541 P30_6 V2 TP07_0 CH A Stop...

Page 102: ...4mA AA4 602 502 P34_2 SEG10 SCK10 TP06_0 CH A Stop LCD COM SEG 4mA AA1 601 499 P34_1 SEG9 SOT10 TP06_0 CH A Stop LCD COM SEG 4mA AB1 599 497 P34_0 SEG8 SIN10 TP06_0 CH A Stop LCD COM SEG 4mA AA2 598 498 P35_7 SEG7 TP06_0 CH A Stop LCD COM SEG 4mA AA3 597 495 P35_6 SEG6 SCK9 TP06_0 CH A Stop LCD COM SEG 4mA AB2 596 496 P35_5 SEG5 SOT9 TP06_0 CH A Stop LCD COM SEG 4mA AB3 595 493 P35_4 SEG4 SIN9 TP0...

Page 103: ..._13 TE10_0 no Tool 4mA AP1 539 446 TAD_12 TE10_0 no Tool 4mA AN2 538 447 TAD_11 TE10_0 no Tool 4mA AP2 536 445 TAD_10 TE10_0 no Tool 4mA AM3 535 444 TAD_9 TE10_0 no Tool 4mA AN3 533 443 TAD_8 TE10_0 no Tool 4mA AN4 532 442 TAD_7 TE10_0 no Tool 4mA AR1 531 441 TAD_6 TE10_0 no Tool 4mA AP4 530 440 TAD_5 TE10_0 no Tool 4mA AT1 529 439 TAD_4 TE10_0 no Tool 4mA AR2 524 436 TAD_3 TE10_0 no Tool 4mA AP3 ...

Page 104: ..._37 TE20_0 C no Tool 4mA AR12 473 396 TDT_36 TE20_0 C no Tool 4mA AT12 472 395 TDT_35 TE20_0 C no Tool 4mA AR13 471 394 TDT_34 TE20_0 C no Tool 4mA AT13 470 392 TDT_33 TE20_0 C no Tool 4mA AV11 468 390 TDT_32 TE20_0 C no Tool 4mA AU13 467 391 TDT_31 TE20_0 C no Tool 4mA AV12 466 388 TDT_30 TE20_0 C no Tool 4mA AU14 465 389 TDT_29 TE20_0 C no Tool 4mA AT14 462 386 TDT_28 TE20_0 C no Tool 4mA AU15 4...

Page 105: ...4mA AV23 416 346 EEWEX TE10_0 no Tool 4mA AU23 415 345 EEOEX TE10_0 no Tool 4mA AV24 414 344 EEBEX_3 TE10_0 no Tool 4mA AU24 413 343 EEBEX_2 TE10_0 no Tool 4mA AT23 412 342 EEBEX_1 TE10_0 no Tool 4mA AT24 410 340 EEBEX_0 TE10_0 no Tool 4mA AU25 409 339 EEA_20 TE10_0 no Tool 4mA AU26 407 338 EEA_19 TE10_0 no Tool 4mA AV25 406 336 EEA_18 TE10_0 no Tool 4mA AV26 404 335 EEA_17 TE10_0 no Tool 4mA AR25...

Page 106: ...96 EED_13 TE20_0 C no Tool 4mA AU35 351 292 EED_12 TE20_0 C no Tool 4mA AT34 350 291 EED_11 TE20_0 C no Tool 4mA AU36 349 290 EED_10 TE20_0 C no Tool 4mA AT35 348 289 EED_9 TE20_0 C no Tool 4mA AT37 344 288 EED_8 TE20_0 C no Tool 4mA AR36 343 287 EED_7 TE20_0 C no Tool 4mA AR37 342 286 EED_6 TE20_0 C no Tool 4mA AP36 341 285 EED_5 TE20_0 C no Tool 4mA AT38 339 283 EED_4 TE20_0 C no Tool 4mA AP35 3...

Page 107: ...5 118 98 VDD5 TS02_0 VDD 5V E32 96 81 VDD5 TS02_0 VDD 5V E28 72 59 VDD5 TS02_0 VDD 5V E20 50 40 VDD5 TS02_0 VDD 5V E12 28 22 VDD5 TS02_0 VDD 5V D8 6 5 VDD5 TS02_0 VDD 5V M5 642 537 VSS5 TS00_0 VSS T5 620 518 VSS5 TS00_0 VSS Y5 600 500 VSS5 TS00_0 VSS AD5 578 482 VSS5 TS00_0 VSS AJ34 306 254 VSS5 TS00_0 VSS AE34 284 235 VSS5 TS00_0 VSS AA34 268 223 VSS5 TS00_0 VSS W34 254 210 VSS5 TS00_0 VSS R34 23...

Page 108: ...20 VCC3C TA10_0 ANA OUT VCC3C Y35 264 219 VCC3C TA10_0 ANA OUT VCC3C Y37 263 218 VCC3C TA10_0 ANA OUT VCC3C Y36 262 217 VCC3C TA10_0 ANA OUT VCC3C 0 0 562 468 VDD3 TS01_0 VDD 0 0 549 455 VDD3 TS01_0 VDD 0 0 527 437 VDD3 TS01_0 VDD 0 0 497 414 VDD3 TS01_0 VDD 0 0 474 397 VDD3 TS01_0 VDD 0 0 463 387 VDD3 TS01_0 VDD 0 0 452 378 VDD3 TS01_0 VDD J5 420 347 VDD3 TS01_0 VDD N5 411 341 VDD3 TS01_0 VDD U5 ...

Page 109: ...c Information 6 Pin Definitions AP20 427 355 VSS3 TS00_0 VSS AP24 405 337 VSS3 TS00_0 VSS AP28 383 318 VSS3 TS00_0 VSS AP30 371 308 VSS3 TS00_0 VSS AT36 355 293 VSS3 TS00_0 VSS AU37 340 284 VSS3 TS00_0 VSS AL34 318 264 VSS3 TS00_0 VSS ...

Page 110: ...A yes A D in D A out 4 mA TP02_0 CH A yes I2C 3 mA TP03_0 Up Dn CH A yes A D in 4 mA TP04_0 Up Dn CH A TTL yes External Bus 4 mA TP05_0 CH A yes SMC A D in 30 mA TP06_0 CH A yes LCD COM SEG 4 mA TP07_0 CH A yes LCD V0 V1 V2 4 mA TP08_0 CH A yes LCD V3 4 mA TC00_0 CH no MCU control TC01_0 Up CH no MCU control TC02_0 Up CH no MCU control TC02_1 CH no MD0 MD1 MD2 TC10_0 no MONCLK 8 mA TA00_0 AVCC TA0...

Page 111: ...95 Chapter 3 MB91460 Series Basic Information 7 I O Circuit Type TE11_0 no Tool 8 mA TE20_0 C no Tool 4 mA TE21_0 Dn ctrl C no Tool 4 mA TE22_0 C no Tool 8 mA TS00_0 VSS TS01_0 VDD TS02_0 VDD 5V ...

Page 112: ...utput Hi Z Input enabled Output Hi Z Input enabled State hold Output State hold Input fixed Output HiZ Input fixed AJ37 314 261 P00_6 D30 D30 AJ36 311 259 P00_5 D29 D29 AJ35 310 258 P00_4 D28 D28 AH36 309 257 P00_3 D27 D27 AH35 308 256 P00_2 D26 D26 AK38 307 255 P00_1 D25 D25 AJ38 305 253 P00_0 D24 D24 AH37 304 252 P01_7 D23 D23 Output Hi Z Input enabled Output Hi Z Input enabled State hold Output...

Page 113: ...8 P04_4 A28 A28 V36 251 205 P04_3 A27 A27 U37 250 206 P04_2 A26 A26 U36 249 203 P04_1 A25 A25 U35 248 204 P04_0 A24 A24 T35 246 202 P05_7 A23 A23 Output Hi Z Input enabled Ext Bus mode Address Output Single Chip mode Output Hi Z Input enabled State hold Output State hold Input fixed Output HiZ Input fixed T38 243 200 P05_6 A22 A22 T37 242 199 P05_5 A21 A21 R38 241 198 P05_4 A20 A20 R37 240 197 P05...

Page 114: ...P09_4 CSX4 CSX4 F38 195 161 P09_3 CSX3 CSX3 G35 194 160 P09_2 CSX2 CSX2 E38 193 159 P09_1 CSX1 CSX1 F37 192 158 P09_0 CSX0 CSX0 E37 190 157 P10_7 Output Hi Z Input enabled Output Hi Z Input enabled State hold Output State hold Input fixed Output HiZ Input fixed G36 189 156 P10_6 MCLKE MCLKE Ext Bus mode MCLKE Output Single Chip mode Output Hi Z Input enabled F36 187 154 P10_5 MCLKI MCLKI MCLKI Out...

Page 115: ...put Hi Z Input enabled Output Hi Z Input enabled State hold Output State hold Input fixed Output HiZ Input fixed A31 142 118 P14_6 ICU6 TIN6 TIN6 TTG14 6 B29 141 117 P14_5 ICU5 TIN5 TIN5 TTG13 5 C29 138 116 P14_4 ICU4 TIN4 TIN4 TTG12 4 D29 137 115 P14_3 ICU3 TIN3 TIN3 TTG11 3 C28 136 114 P14_2 ICU2 TIN2 TIN2 TTG10 2 D28 135 113 P14_1 ICU1 TIN1 TIN1 TTG9 1 A30 134 112 P14_0 ICU0 TIN0 TIN0 TTG8 0 A2...

Page 116: ...0 89 73 P19_7 Output Hi Z Input enabled Output Hi Z Input enabled State hold Output State hold Input fixed Output HiZ Input fixed A20 88 74 P19_6 SCK5 CK5 C19 87 71 P19_5 SOT5 A19 86 72 P19_4 SIN5 D19 85 70 P19_3 B19 84 69 P19_2 SCK4 CK4 D18 83 68 P19_1 SOT4 A18 82 67 P19_0 SIN4 A17 80 65 P20_7 Output Hi Z Input enabled Output Hi Z Input enabled State hold Output State hold Input fixed Output HiZ ...

Page 117: ... STOP Input enabled if PFR is set for Ext INT B11 51 41 P22_1 TX4 A12 48 39 P22_0 RX4 INT12 STOP Input enabled if PFR is set for Ext INT D12 47 38 P23_7 TX3 Output Hi Z Input enabled Output Hi Z Input enabled State hold Output State hold Input fixed Output HiZ Input fixed A11 46 37 P23_6 RX3 INT11 STOP Input enabled if PFR is set for Ext INT D11 45 36 P23_5 TX2 C12 44 35 P23_4 RX2 INT10 STOP Input...

Page 118: ...d State hold Output State hold Input fixed Output HiZ Input fixed G3 677 565 P26_6 SMC2P3 AN30 E1 675 562 P26_5 SMC1M 3 AN29 G2 674 563 P26_4 SMC1P3 AN28 F1 673 560 P26_3 SMC2M 2 AN27 H2 672 561 P26_2 SMC2P2 AN26 H4 668 558 P26_1 SMC1M 2 AN25 J4 666 557 P26_0 SMC1P2 AN24 H3 667 556 P27_7 SMC2M 1 AN23 Output Hi Z Input enabled Output Hi Z Input enabled State hold Output State hold Input fixed Outpu...

Page 119: ...tate hold Output State hold Input fixed Output HiZ Input fixed P2 638 533 P31_6 SEG38 P3 635 529 P31_5 SEG37 R2 634 530 P31_4 SEG36 R3 633 527 P31_3 SEG35 T2 632 528 P31_2 SEG34 N1 631 526 P31_1 SEG33 P1 629 524 P31_0 SEG32 R4 628 525 P32_7 SEG31 Output Hi Z Input enabled Output Hi Z Input enabled State hold Output State hold Input fixed Output HiZ Input fixed T4 626 523 P32_6 SEG30 SCK15 U2 624 5...

Page 120: ...CK10 AA1 601 499 P34_1 SEG9 SOT10 AB1 599 497 P34_0 SEG8 SIN10 AA2 598 498 P35_7 SEG7 Output Hi Z Input enabled Output Hi Z Input enabled State hold Output State hold Input fixed Output HiZ Input fixed AA3 597 495 P35_6 SEG6 SCK9 AB2 596 496 P35_5 SEG5 SOT9 AB3 595 493 P35_4 SEG4 SIN9 AB4 594 494 P35_3 SEG3 AC4 592 492 P35_2 SEG2 SCK8 AC1 589 489 P35_1 SEG1 SOT8 AC2 588 490 P35_0 SEG0 SIN8 AD1 587...

Page 121: ...ent 32 bit 16 bit bus converter realizes the interface between CPU and peripheral functions Harvard Princeton bus converter connects both of I bus and D bus and realizes the interface between CPU and bus controller Figure 1 1 Connection Diagram of Internal Architecture FR CPU Harvard Princeton Bus Converter Embedded I Cache Embedded RAM Embedded Flash or ROM Embedded RAM Bus Converter 16 bit 32 bi...

Page 122: ... x 32 bit multiplication 5 cycles 16 bit x 16 bit multiplication 3 cycles Enhanced interrupt processing function High speed respond 6 cycles Support of multiple interrupts Level mask function 16 levels Enhanced instruction for I O operation Transfer instruction between memories Bit processing instruction Highly efficient code Length of base instruction words 16 bits Standby mode Low power consumpt...

Page 123: ...struction In addition a slow instruction degrades instruction execution speed 4 32 bit 16 bit Bus Converter This converter generates the interface between D bus which executes 32 bit high speed access and R bus which executes 16 bit access in order to realize data access from CPU to peripheral functions If 32 bit access comes from CPU this converter converts the access into two 16 bit accesses to ...

Page 124: ...and write to memory This is also used for read and write to peripheral functions I O within chip Load and store consist of 3 type access lengths including byte half word and word In addition to general register indirect memory addressing some instructions allow register indirect memory addressing with displacement or with register increment decrement Branch This is the instruction for branch call ...

Page 125: ... Structure of Bit Ordering Byte Ordering FR60 uses big endian as byte ordering Figure 7 2 Bit Structure of Byte Ordering bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LSB MSB Memory MSB bit31 23 15 7 LSB 0 10101010 11001100 11001100 11111111 11111111 00010001 00010001 bit 7 0 10101010 n address n 1 address n 2 address n 3 address ...

Page 126: ...des the following alignment for addresses depending on data width when executing data access Word access Address is multiplied by 4 Lowest order 2 bits are mandatorily 00 Half word access Address is multiplied by 2 Lowest order bit is mandatorily 0 Byte access Address is multiplied by 1 Upon the word and half word data accesses some bits mandatorily become 0 for computing results of effective addr...

Page 127: ...e following areas are used for I O These spaces are referred to as direct addressing area where you can specify direct operand address by the instruction These direct areas vary by data size to be accessed Byte access 0 0FFH Half word access 0 1FFH Word access 0 3FFH 0000 0000H 0000 0100H 0000 0200H 0000 0400H Direct addressing area 000F FC00H 000F FFFFH FFFF FFFFH Byte data Half word data Word da...

Page 128: ...112 Chapter 4 CPU Architecture 9 Addressing ...

Page 129: ...nter R15 Stack pointer Initial values by reset are indeterminate for R0 through R14 Initial value by reset is 00000000H SSP value for R15 2 Dedicated Registers Dedicated registers consist of program counter PC program status PS table base register TBR return pointer RP system stack pointer SSP user stack pointer USP and multiply divide register MDH MDL Figure 2 1 Dedicated Registers List XXXX XXXX...

Page 130: ... Structure of Program Status PS CCR Condition Code Register Figure 2 4 Structure of Condition Code Register CCR Bit 5 S Stack flag This bit specifies stack pointer This bit becomes 0 by reset After using R15 as USP write 0 before executing RETI instruction Bit 4 I Interrupt enable flag This bit enables and disables user interrupt request S Description 0 Uses R15 as SSP Upon generating EIT this bit...

Page 131: ...sion step division is assured to be restarted by saving and returning PS register value Initial status by reset is indeterminate for D1 and D0 bits Upon executing DIV0S instruction these bits are set by referring to dividend and divisor Upon executing DIV0U instruction these bits mandatorily become 00 Bit 8 T Step trace trap flag This bit is the flag to specify whether to enable step trace trap or...

Page 132: ...epted only if it s priority is higher than the level For level value the highest priority is 0 00000B and the lowest priority is 31 11111B Program has some restrictions on configurable data When original value is between 16 and 31 Configurable new values are the value between 16 and 31 If you execute the instruction to set the value between 0 and 15 specified value 16 value is set When original va...

Page 133: ...e executed If user interrupt is received If step execution is executed If data event or emulator menu is broken 1 D0 or D1 flag is updated in first 2 EIT processing routine user interrupt or emulator is executed 3 After returning from EIT it executes DIV0U DIV0S instruction and updates D0 D1 flag to the same value as 1 When user interrupt is generated if you execute each instruction of ORCCR STILM...

Page 134: ...ng RET RP data are set in this PC 2 5 SSP System Stack Pointer System stack pointer SSP is used for the pointer which receives EIT and indicates stack to save return data for return operation System stack pointer SSP consists of 32 bits Figure 2 9 Bit Structure of System Stack Pointer SSP When S flag is 0 it works as R15 You can explicitly specify SSP Upon generating EIT it is used for the pointer...

Page 135: ...ify USP You can not use it for RETI instruction This pointer saves and returns PC and PS values at the position where system stack pointer SSP indicates After interrupt it stores PC in address where SSP indicates and PS in SSP 4 address Figure 2 11 Interrupt Stack 31 Initial value USP 00000000H 0 Example Before interrupt After interrupt SSP SSP 80000000H 7FFFFFFCH 7FFFFFF8H 80000000H 7FFFFFFCH 7FF...

Page 136: ...ultiplication When 32 bits x 32 bits multiplication operation results of 64 bits are stored in multiplication division store register as the following allocation MDH Upper 32 bits MDL Lower 32 bits When 16 bits x 16 bits multiplication results are stored as follows MDH Indeterminate MDL Results of 32 bits At the executing division Upon starting operation dividend is stored in MDL By computing divi...

Page 137: ...e event which is generated in association with active context Some trap is specified by program such as system call It is returned to the instruction following the instruction which triggered the trap 2 Features Supports multiple interrupts Level mask function for interrupt User can use 15 level Trap instruction INT EIT for emulator trigger hardware software 3 EIT Trigger Reset User interrupt peri...

Page 138: ...Table Page No 73 Address arithmetic is as follows Vector address TBR Offset value TBR 03FCH 4 x Vector number No Lower two bits as the result of addition are always used for 00 000FFC00H through 000FFFFFH areas are initial values of vector table by reset If you rewrite the TBR value the mode and reset vectors always use the fixed address of 000FFFF8H 000FFFFCH Table 5 1 Interrupt Level of EIT Leve...

Page 139: ...t of EIT triggers Table 7 1 Priority Level of Receipt of EIT Triggers and Mask for Other Triggers Priority for accepting EITs EIT Masking of other EITs 1 Reset All EITs are cleared 2 Instruction Break Other EITs are canceled ILM 4 3 INTE instruction Other EITs are canceled ILM 4 4 Undefined instruction exception Other EITs are canceled I flag 0 5 INT instruction Coprocessor exceptions I flag 0 6 M...

Page 140: ...ocessing Figure 7 1 Multiple EITs Process Priority High Generation of NMI Middle Execution of INT instruction INT instruction handler 2 Second execution Main routine NMI handler 1 First execution 3 Third execution Low Execution of user interrupt User interrupt handler ...

Page 141: ...vel Level mask value the interrupt request is masked without receipt Where Interrupt level Level mask value it goes forward to Step 4 4 When selected interrupt request is maskable interrupt if I flag is 0 its Interrupt request is masked without receipt and if I flag is 1 it goes forward to Step 5 5 If conditions above are satisfied interrupt requests are received between instruction processes If u...

Page 142: ... code register CCR in the program status PS 6 The value TBR 3FCH 4 x u8 is stored in the program counter PC 8 3 Operation of INTE Instruction INTE instruction is operated as follows Branches to vector interrupt handler of vector number 9 Operation 1 The contents of the program status PS are saved to the system stack 2 The address of the next instruction is saved to the system stack 3 The value of ...

Page 143: ...ble step trace trap user interrupt is disabled In addition EIT will not be generated by INTE instruction FR60 generates traps from next instruction to instruction which set T flag 8 5 Operation of Undefined instruction Exception If any undefined instruction is detected upon decoding instruction undefined instruction exception is generated Condition for detecting undefined instruction exception Upo...

Page 144: ...time Operation 1 The contents of the program status PS are saved to the system stack 2 The address of the instruction that caused the undefined instruction exception is saved to the system stack 3 The value of the system stack pointer SSP is reduced by 8 4 The value 0 is written to the S flag in the condition code register CCR in the program status PS 5 The value TBR 3DCH is stored in the program ...

Page 145: ...t has no valid instruction NOP instruction must be entered Example In conditional branch instruction regardless of whether branch parameter is approved or not instructions located in delay slot are executed In delay branch instruction execution sequence of some instructions seems opposite however it only applies to updating process on the PC Any other operation register update look up is executed ...

Page 146: ...instructions within delay slot Example 3 4 CALL D Instruction When RP is referred using the instruction within delay slot of CALL D instruction the data updated by CALL D instruction is read out Example LDI 32 Label R0 JMP D R0 Branches to Label LDI 8 0 R0 Not affect any branched address RET D Branches to the address previously specified in RP MOV R8 RP Not affect any return operation ADD 1 R0 Cha...

Page 147: ...is changed 1 cycle instruction indicates instructions whose number of cycles column in the instruction list table is described with 1 a b c or d 4 2 Step Trace Trap Step trace trap is not generated between the execution of branch instruction with delay slot and delay slot 4 3 Interrupt Interrupt is not acceptable between the execution of branch instruction with delay slot and delay slot 4 4 Undefi...

Page 148: ...e the branch instruction with delay slot where NOP is described because appropriate instruction cannot be entered it can increase efficiency of instruction code Select the operation with delay slot when valid instruction can be set in delay slot Otherwise select the operation without delay slot This selection enables FR60 to satisfy both of execution rate and code efficiency JMP Ri CALL label12 CA...

Page 149: ...e STOP to the RUN state waiting until clock oscillation is stabilized Oscillation stabilization wait reset State for waiting until the clock oscillation is stabilized after INIT Operation initialization reset RST State where the program is initialized Setting initialization reset INIT State where all settings are initialized Standby mode Low power consumption mode SLEEP and STOP above are standby ...

Page 150: ...lation stabilization wait 4 Cancel of reset RST 5 Software reset RST 6 Sleep Writing instruction 7 Stop Writing instruction 8 Interrupt 9 External interrupt requiring no clock 10 Switching from main to sub Writing instruction 11 Switching from sub to main Writing instruction 12 Watchdog reset INIT 13 Sub sleep Writing instruction Priority of transition request Highest priority Setting initializati...

Page 151: ...Upon generation of specific valid interrupt requests requiring no clock active oscillation timer interrupt or main clock oscillation stabilization timer interrupt request the oscillation stabilization wait RUN state is entered Upon generation of the setting initialization reset request by the external INITX pin the setting initialization reset state INIT is entered Upon generation of the operation...

Page 152: ...tion initialization reset sequence Upon returning from setting initialization reset INIT this state executes the setting initialization reset sequence Upon generation of the setting initialization reset request by the external INITX pin the setting initialization reset state INIT is entered 3 7 Setting initialization Reset INIT This is the state where all settings are initialized Upon receipt of r...

Page 153: ...137 Chapter 8 Device State Transition 3 State Transition Diagram ...

Page 154: ...138 Chapter 8 Device State Transition 3 State Transition Diagram ...

Page 155: ...ialization reset INIT Watchdog reset Settings initialization reset INIT Software reset Operation initialization reset RST Low Voltage reset Setting initialization reset INIT Although a watchdog reset triggers the same settings initialization reset INIT as the INITX pin input it does not initialize the oscillation stabilization time selection bits OS 1 0 and reset cause flags INIT HSTB WDOG ERST SR...

Page 156: ...rrupts STOP 0 1 STCR bit7 SLEEP 0 1 STCR bit7 OSCD1 0 1 STCR bit1 HIZ 0 1 STCR bit0 State transition control circuit reset related State transition control circuit 0 1 RSRR bit5 No watchdog timeout Watchdog timeout INIT occurred 0 1 RSRR bit3 No software reset RST Software reset RST occurred 0 1 RSRR bit7 INIT No INIT pin input Watchdog timer 0 1 STCR bit4 Trigger software reset Do not trigger sof...

Page 157: ...curred flag HSTB is cleared to 0 after reading Bit5 Watchdog reset occurred flag Indicates whether a reset INIT was triggered by the watchdog timer The watchdog reset occurred flag WDOG is cleared to 0 after reading Bit4 External reset occurred flag Indicates whether a reset RST was triggered by the RST pin input The external reset occurred flag ERST is cleared to 0 after reading Bit3 Software res...

Page 158: ...ccurred flag LINIT is cleared to 0 after reading Bit1 0 Watchdog period selection The watchdog period selection bits WT 1 0 can set the period of the watchdog timer to the following F x 220 to 221 F x 222 to 223 F x 224 to 225 F x 226 to 227 See Chapter 20 Software Watchdog Timer Page No 273 for details SRST Meaning 0 No RST has been triggered by a software reset 1 RST has been triggered by a soft...

Page 159: ...e software reset bit triggers a software reset Note that negative logic is used The read value is always 1 Bit3 2 Oscillation stabilization time selection The oscillation stabilization time selection bits OS 1 0 set the oscillation stabilization time as follows F2 x 21 F2 x 211 F2 x 216 F2 x 222 The count is supplied by the timebase counter Initialized to 00 F2 x 21 main clock by a reset triggered...

Page 160: ...ved bits Always set these bits to 00000 If a value other than 00000 is set the operation of the MCU is not guaranteed Bit26 Internal ROM enable Specifies whether to enable the internal ROM area Always set to 1 Bit25 24 Bus width setting This sets the bus width for external bus mode Bit23 0 Undefined bits 4 5 Reset Vector The MCU starts program execution from the address specified by the mode vecto...

Page 161: ...XED Mode Reset Vector ROMA ROM access area WTH 1 0 Bus width Remarks MD2 MD1 MD0 0 0 0 Internal Yes 1 Internal 10 32bit Fixed Mode Data is 0x06 No 0 External 00 8bit 01 16bit 10 32bit 11 Single Setting not supported 1 Internal 00 8bit 01 16bit 10 32bit 11 Single 0 0 1 External 0 External 00 8bit 01 16bit 10 32bit 11 Single Setting not supported 1 Internal 00 8bit 01 16bit 10 32bit 11 Single Settin...

Page 162: ...vel and initializes all settings This type of reset is called the settings initialization reset INIT A settings initialization reset INIT triggered by INIT pin input has the highest priority of all resets and has priority over all other inputs operations and states When a settings initialization reset INIT occurs it is followed by an operation reset RST after the oscillation stabilization time ela...

Page 163: ...d 1 Removal of settings initialization reset INIT 2 Set operation reset RST state and start internal clock 3 Clear operation reset RST state and change to normal operation RUN 4 Read mode vector from address 000FFFF8H 5 Write mode vector to MODR mode register 6 Read reset vector from address 000FFFFCH 7 Write reset vector in PC program counter Start program execution from the address specified by ...

Page 164: ... when an operation reset RST occurs 6 3 Flag When watchdog reset request triggers a settings initialization reset INIT the watchdog timeout flag RSRR WDOG is set to 1 6 4 Reset Level This reset has the maximum reset level and initializes all settings This type of reset is called the settings initialization reset INIT When a settings initialization reset INIT occurs it is followed by an operation r...

Page 165: ...m and is called an operation reset RST The following section lists the main items initialized by an operation reset RST 7 5 Items Initialized by Operation Reset RST Program operation CPU and internal bus Content of registers in peripheral circuits I O port settings Device operation mode bus mode and external bus width setting 7 6 Reset Cancellation Sequence After cancellation removal of the operat...

Page 166: ...n enable bit TBCR SYNCR to 0 specifies normal reset mode Normal reset mode is the default setting after a settings initialization reset INIT 8 2 Synchronous Reset Operation Synchronous reset operation refers to the mode when the device does not go to the operation reset RST state after a operation reset RST request until after all bus access has halted In synchronous reset mode the device does not...

Page 167: ... other areas is disabled External pins are used either by the peripheral functions or as general purpose ports Pins cannot be used as bus pins This mode can not be used when using the fixed mode reset vector as implemented on most of the MB91460 series devices Internal ROM external bus mode In this mode internal I O internal RAM and internal ROM are available and access to areas for which external...

Page 168: ...chronous reset operation enable bit TBCR SYNCR when an operation reset RST is triggered by a software reset request the operation reset RST does not occur until all bus access halts Accordingly there may be a long delay before the operation reset RST occurs depending on the bus usage Settings initialization reset INIT A settings initialization reset INIT invokes an operation reset RST after the os...

Page 169: ...153 Chapter 9 Reset 10 Caution ...

Page 170: ...154 Chapter 9 Reset 10 Caution ...

Page 171: ... operation reset RST Stop mode Device state in stop mode The overall device halts Internal circuits halt with some exceptions Internal clock signals halt with some exceptions Whether or not the oscillation circuit halts can be controlled by a setting programmable All external pins can be set to high impedance programmable excludes some pins Transition to stop mode Stop mode is invoked by the progr...

Page 172: ... Watchdog timer SRST 0 1 STCR bit4 Generate software reset Do not generate software reset INIT Stop signal Clock control Pin control Initialize settings INIT Initialize operation RST Internal interrupts external interrupts STOP 0 1 STCR bit7 Do not change to stop mode Change to stop mode SLEEP 0 1 STCR bit7 Do not change to sleep mode Change to sleep mode OSCD1 0 1 STCR bit0 Do not halt main clock...

Page 173: ... setting is high impedance Bit4 Software reset SRST Setting this bit to 0 invokes a software reset Bit3 2 Oscillation stabilization time selection OS 1 0 Setting these bits in the range 00 11 sets the oscillation stabilization time to use after recovering from stop mode An INIT pin input reset or watchdog reset initialize this setting to its initial value See Chapter 18 Timebase Counter Page No 24...

Page 174: ...ion for timebase timer Writing a value in the range 000 111 to these bits selects the interval time for the timebase timer F x 211 x 212 x 213 x 222 x 223 x 224 x 225 x 226 Bit2 Reserved Writing does not affect the operation The read value is undefined Bit1 Enable synchronous reset operation Selects a normal reset 0 or a synchronous reset 1 Bit0 Enable synchronous standby operation OSCD1 Operation...

Page 175: ...and internal bus halt Circuits that halt during sleep mode Bit search module All internal memory inclusive I cache Internal external bus Circuits that do not halt during sleep mode Oscillation circuit main PLL if enabled Clock generation control circuit Interrupt controller External interrupts DMA Peripherals Recovery and other items Generation of an interrupt request that is currently enabled cha...

Page 176: ... selected as the clock source Pin states High impedance or maintain previous state When pin outputs are set to go to high impedance during stop mode High impedance output Pins that are set as general purpose ports and pins that have been selected for use by peripheral functions When pin outputs are set to maintain their previous states during stop mode Maintain previous state Pins that are set as ...

Page 177: ...heral function Synchronous standby settings Timebase timer control register TBCR See 7 1 Change to sleep mode Standby control register STCR See 7 1 Operational restrictions See 8 Caution Page No 165 Table 6 2 Settings Required to Change to Stop Mode Setting Setting register Setting procedure Selects the oscillation stabilization wait time See Chapter 18 Timebase Counter Page No 249 Interrupt setti...

Page 178: ...llation during stop mode Use the main clock oscillation stop bit STCR OSCD1 7 5 How do I recover from sleep mode Two methods are available to recover from sleep mode Generation of a valid interrupt request changes to RUN mode restores normal operation If using interrupt processing remember to set the I flag I interrupt level mask register ILM and interrupt control register ICR An INIT pin input or...

Page 179: ...ion timer when oscillation not halted Real time clock when oscillation not halted If using interrupt processing remember to set the I flag I interrupt level mask register ILM and interrupt control register ICR Input to the INIT pin invokes an initialization reset INIT followed by an oscillation stabilization delay and then an operation reset RST In the case of an INIT pin input an oscillation stab...

Page 180: ...164 Chapter 10 Standby 7 Q A ...

Page 181: ...g are the same as for normal operation Also you do not necessarily have to halt the PLL oscillation If interrupts are disabled in the interrupt control register ICR 00011111B the device will not recover from stop or sleep mode when an interrupt occurs Pin high impedance control in stop mode Setting the high impedance bit STCR HIZ to 1 sets pin outputs to high impedance during stop mode If the high...

Page 182: ...166 Chapter 10 Standby 8 Caution ...

Page 183: ...64 bit read mode and 16 or 32 bit read write mode for programming Support of external SRAM for emulation devices with 1 1 timing transparency same wait cycles Measures for FLASH macro test and parallel programming support 3 General Purpose RAM Zero wait cycle access code one wait cycle access data to shared code data memory up to 64 kByte also referenced as I D RAM 4 Instruction Cache and Data Buf...

Page 184: ...nd word FMCR and FMWT2 registers are not available on MB91V460 The initial values of the waitcycle setting register FMWT differs between the flash less evaluation device MB91V460 and devices with embedded flash memory Notes 1 Initial value on MB91V460 2 Initial value on MB91F467DA Table 7 1 FLASH IF Registers Summary Address Register Block 0 1 2 3 7000H FMCS R W 01101000 FMCR R W 0000 FCHCR R W 00...

Page 185: ...ccess default 1 Asynchronous FLASH access 0 Disable FMV FRV and enable FLASH access at mode vector address 1 Output the fixed mode or reset vector at address hit default ASYNC FIXE BIRE RDYEG RDY RDYI RW16 LPM Bit no Read write R W R W R W R R R W R W R W Default value 0 1 1 0 1 0 0 0 Control Register byte 0 Address 7000H 31 30 29 28 27 26 25 24 FMCS LOCK PHASE PF2I RD64 Bit no Read write R W R W ...

Page 186: ...auto algorithm has been completed The RDY bit is read only status information Remark The function of this status bit is not guaranteed when running the CPU on frequencies lower than 1MHz BIT 26 RDYI RDY output force This bit is reserved for FLASH test Do not set this bit BIT 25 RW16 16 bit Read Write enable to FLASH This bit is cleared after reset There is a 32 bit read and write access to the FLA...

Page 187: ...n device MB91V460 BIT 19 LOCK ALEH auto update lock FLASH memories embedded on the MB91460 series require a certain timing between ATDIN falling edge and EQIN rising edge This timing is named tALEH and has usually the same length as the ATDIN duration By writing the setting of ATDIN length to the FMWT ATD 2 0 bits the FMWT2 ALEH 2 0 bits will be updated auto matically to the same setting To avoid ...

Page 188: ...and write access to the FLASH memory is enabled by de fault Setting of the RD64 bit implies switching from 32 bit into 64 bit mode Writing data to the flash memory is not supported in the 64 bit read only mode Important remark It is not allowed to switch between the 16 bit the 32 bit and the 64 bit mode while reading instructions or data from the FLASH memory FLASH Cache Control Register FCHCR BIT...

Page 189: ...not available on MB91460 series BIT 5 PFEN PreFetch ENable This bit is cleared after reset The prefetch of instructions is disabled by default Setting the PFEN bit enables the code prefetch from the next word on instruction address IA 4 Prefetch eliminates any latency in the code fetch path of the MCU to the FLASH memory for linear code When switching on 64 bit read mode RD64 1 then prefetch will ...

Page 190: ...ct of this algorithm is that the restricted amount of cache entries is utilized more efficiently Usually the same performance can be reached with half the cache size Or in other words the cache is as same efficient as it would have the doubled size The efficiency of the PFMC algorithm depends on the structure of the application BIT 3 LOCK Global lock of cache entries This bit is cleared during res...

Page 191: ... 0x7 on MB91V460 and 0x5 on MB91F467DA EQ 3 0 setting is 0xF on MB91V460 and 0xD on MB91F467DA FMWT2 is not available on MB91V460 BIT 31 30 WTP 1 0 Wait cycles for FLASH in page access WTP is set to 3 after reset 00 0kByte Cache disabled 01 4kByte 1024 entries 10 8kByte 2048 entries 11 16kByte 4096 entries default WTP1 WTP0 WEXH1 WEXH0 WTC3 WTC2 WTC1 WTC0 Bit no Read write R W R W R W R W R W R W ...

Page 192: ...D defaults to 4 clock cycles MB91F467DA ATD is set to 5 after reset ATD defaults to 3 clock cycles ATD controls the timing of the ATDIN signal for FLASH access The ATD configuration is in units of half clock cycles The effective high duration of ATDIN equals to tATDIN ATD 1 0 5 clock cycles BIT 19 16 EQ 3 0 Duration of the EQIN signal for FLASH memory access MB91V460 EQ is set to 15 after reset EQ...

Page 193: ...cycles WTC 1 BIT 2 0 PS 2 0 Page size definition for Page Mode FLASH PS is set to 0 after reset Page Mode FLASH is disabled by default This setting defines the page size to 2 PS in number of bytes E g for Am29PL320D MBM29PL3200 with a page size of 16 byte the value of PS has to be set to 4 Embedded FLASH memories on MB91460 series do not support page mode Symbol Length Setup tATD 1 5 cycles ATD 2 ...

Page 194: ...is located outside the FLASH region thus initially the whole FLASH region will be cached If the FCHCR_REN bit is cleared the address range is defined by the address given by FCHA0 masked with the bits set to 1 in FCHA1 Example 1 Point and mask range definition FCHCR_REN 0 FCHA0 0x000F A300 FCHA1 0x0000 FFFF The non cacheable area is defined from 0x000F 0000 to 0x000F FFFF Example 2 Point to point ...

Page 195: ... setting the RAM mode To turn off the instruction cache after turning it on once be sure to use the subroutine shown in Section 4 2 4 Settings for handling the I Cache 2 Main body structure FR basic instruction length 2 bytes Block arrangement system 2 way set associative system Block 128 blocks per way 16 bytes per block 4 sub blocks 4 bytes per sub block 1 bus access unit Figure 2 1 Instruction ...

Page 196: ...2 When the requested instruction data does not exist in the cache miss the CPU and cache obtain the data loaded by external access at the same time Bits 7 to 4 SBV3 to SBV0 Sub block valid bits When SBV contains 1 the corresponding sub block holds the current instruction data at the address located by the tag Each sub block usually holds two instructions including immediate value transfer instruct...

Page 197: ... lock states access to external memory takes place after losing one cycle used for evaluating the cache miss Control register structure ISIZE bits 1 to 0 SIZE1 and SIZE0 These bits set the cache capacity The combination of the settings determines the cache size IRAM size and the address map in RAM mode as shown in Figure I CACHE 3 When the cache size is changed be sure to flush the cache and relea...

Page 198: ...les or disables auto locking for each entry in the instruction cache An entry accessed but resulting in a miss with the EOLK bit containing 1 is locked when the entry lock bit in the cache tag is set to 1 by hardware Once locked the entry is not updated at any cache miss that follows until it is unlocked Note however that invalid sub blocks are updated To ensure the entry lock set this bit after f...

Page 199: ...183 Chapter 12 Instruction Cache 2 Main body structure Figure 2 3 I Cache Address Map ...

Page 200: ...184 Chapter 12 Instruction Cache 2 Main body structure Figure 2 4 I Cacheable Area ...

Page 201: ...state is held Rewriting is impossible while the cache is disabled The preceding state is held entry lock release is required TAG Valid Bit Contents undefined The preceding state is held Flushingis possible while the cache is disabled All entries are invalid RAM Normal Mode The preceding state is held Flushing is possible while the cache is disabled The preceding state is held Control Register Glob...

Page 202: ...tializing To use the I Cache first clear the cache contents Erase the old data by setting the register FLUSH bit and ELKR bit to 1 Idi 0x000003e7 r0 I Cache control register address Idi 0B00000110 r1 FLUSH bit bit 1 ELKR bit bit 2 stb r1 r0 Writing to register The cache is now initialized 2 Enabling turning ON cache To enable the I Cache set the ENAB bit to 1 Idi 0x000003e7 r0 I Cache control regi...

Page 203: ... Locking specific cached instructions To lock a specific group of instructions e g subroutines in the cache set the EOLK bit to 1 before executing such instructions Instructions locked in this manner are accessed rapidly as if using high speed internal ROM Idi 0x000003e7 r0 I Cache control register address Idi 0B00001001 r1 ENAB bit bit 0 EOLK bit bit 3 stb r1 r0 Writing to register The above inst...

Page 204: ... Chapter 12 Instruction Cache 5 Settings for handling the I Cache Only lock information is released locked instructions are replaced sequentially with new instructions according to the state of the LRU bit ...

Page 205: ... FCL MAIN divided by 2 Subclock FCL SUB Operating clocks Selectable from 16 different speeds CPU clock CLKB F 1 2 3 4 5 6 7 8 16 The clock used by the CPU internal memory and internal buses The circuits that use this clock are as follows CPU internal RAM internal ROM bit search module I bus D bus F bus X bus On chip debug support unit DSU Peripheral clock CLKP F 1 2 3 4 5 6 7 8 16 The clock used b...

Page 206: ...ock selection enabled OSCDS1 0 1 OSCCR bit0 Main clock continues to run in subclock mode Main clock halts in subclock mode X0 X1 X1A X0A FCLKT CLKS1 CLKS0 CLKR bit6 4 Permitted change 00 01 10 11 Main clock divided by 2 main clock mode Main clock divided by 2 main clock mode Main PLL main clock mode Subclock subclock mode 00 01 10 01 11 00 10 00 11 01 OSCD2 0 1 STCR bit1 Continue oscillation in st...

Page 207: ...ging the PLL state see chapter Clock Auto Gear Up Down on P 213 If the main clock oscillation is halted STCR OSCD1 1 the main PLL halts during stop mode even if the PLL enable bit PLL1EN is set to 1 If main PLL operation is enabled PLL1EN 1 the main clock operates using the PLL after recovering from stop mode See the explanation for the clock source selection bits bits 1 0 for details of changing ...

Page 208: ...he subclock selection enable bit SCKEN is 0 See table for details Example To select the subclock after an INIT reset first write 01B and then write 11B subclock See 8 Caution Page No 205 Table 4 1 Cases When the CLKS1 and CLKS0 Bits May or May Not be Modified Modify permitted Modify not permitted 00 01 or 10 00 11 01 11 or 00 01 10 10 00 10 01 or 11 11 01 11 00 or 10 ...

Page 209: ...ock used by the CPU internal memory and internal buses CLKB The 16 options listed in the table are available Do not set a division ratio that exceeds the maximum operating frequency of the device Bit3 0 CLKP division selection 7 6 5 4 3 2 1 0 bit B3 B2 B1 B0 P3 P2 P1 P0 0 0 0 0 0 0 1 1 Initial value INIT pin input watchdog reset X X X X X X X X Initial value software reset R W R W R W R W R W R W ...

Page 210: ...atio for the clock used by the peripheral circuits and peripheral bus CLKP The 16 options listed in the table are available Do not set a division ratio that exceeds the maximum operating frequency of the MCU 1010 Φ 11 1011 Φ 12 1100 Φ 13 1101 Φ 14 1110 Φ 15 1111 Φ 16 ...

Page 211: ... listed in the table are available Do not set a division ratio that exceeds the maximum operating frequency of the device If you modify the CLKP division selection bits the new division ratio applies from the next clock after the setting is modified Bit3 0 Reserved bit Always write 0 to this bit The read value is the value written 7 6 5 4 3 2 1 0 bit T3 T2 T1 T0 0 0 0 0 0 0 0 0 Initial value INIT ...

Page 212: ... chapter Clock Monitor Page No 941 about information about this function Bit3 0 Clock Source Selection 7 6 5 4 3 2 1 0 bit EDSUEN PLLLOCK RCSEL MONCKI CSC3 CSC2 CSC1 CSC0 0 X 0 0 0 0 0 0 Initial value INIT pin input watchdog reset X X X X X X X X Initial value software reset R W R R W R W R W R W R W R W Attribute EDSUEN Function 0 EDSU MPU is clock disabled Initial value 1 EDSU MPU is clock enabl...

Page 213: ...197 Chapter 13 Clock Control 4 Registers 1 Subclock Calibration is sourced by RC Oscillation 0 LCD Controller is sourced by Sub Oscillation 1 LCD Controller is sourced by RC Oscillation ...

Page 214: ... 00 01 10 specifying the main clock to halt during subclock mode OSCDS1 1 is prohibited See 8 Caution Page No 205 7 6 5 4 3 2 1 0 bit OSCDS2 OSCDS1 X X X X 0 0 0 0 Initial value INIT pin input watchdog reset X X X X X X X X Initial value software reset RX WX RX WX RX WX RX WX RX WX RX WX R W R W Attribute OSCDS2 Operation when written to Read value meaning 0 Does not halt sub clock during subclock...

Page 215: ...vide ratios for operating clocks CLKB CLKP CLKT Setup operating clocks 4 Wait for main PLL to lock See oscillation stabilization wait chapter 1 Select sub clock mode Select clock source CLKS 1 0 11 5 Select main PLL mode Select clock source CLKS 1 0 00 Select clock source CLKS 1 0 11 4 Wait for main PLL to lock See oscillation stabilization wait chapter 2 Halt main PLL PLL1EN 0 halt main clock osc...

Page 216: ...the main PLL multiplier setting during normal operation first change the clock source to something other than the main PLL As in the above case after changing the multiplier setting wait for the main PLL lock time before changing the clock source The main PLL multiplier setting can be changed while the main PLL is in use In this case the MCU automatically goes to the oscillation stabilization wait...

Page 217: ...LKR See 7 3 Table 6 2 Settings for Operating Using the Main PLL Setting Setting register Setting procedure Main PLL operation enable Clock source control register CLKR See 7 1 Clock source selection See 7 3 Table 6 3 Settings for Operating Using the Subclock Setting Setting register Setting procedure Subclock selection enable Clock source control register CLKR See 7 1 Clock source selection See 7 ...

Page 218: ...rce selection bits CLKR CLKS 1 0 to select main clock divided by 2 main PLL or the subclock as the operating clock source Operation Main PLL operation enable bit PLL1EN To halt the main PLL Set to 0 To enable operation of the main PLL Set to 1 Operation Subclock selection enable bit SCKEN Subclock selection prohibited Set to 0 To enable selection of the subclock Set to 1 Operating clock source Clo...

Page 219: ...iplier ratio CLKP division ratio selection bits P 3 0 Example frequency When FΦ 32MHz When FΦ 16MHz To select no division Set to 0000 FCLKP 32 0MHz FCLKP 16 0MHz To select divide by 2 Set to 0001 FCLKP 16 0MHz FCLKP 8 00MHz To select divide by 3 Set to 0010 FCLKP 10 6MHz FCLKP 5 33MHz To select divide by 4 Set to 0011 FCLKP 8 00MHz FCLKP 4 00MHz To select divide by 5 Set to 0100 FCLKP 6 40MHz FCLK...

Page 220: ...e 8 Caution Page No 205 7 7 How do I halt the sub clock in main clock mode Operation in subclock mode Halt main clock oscillation in subclock mode bit OSCDS1 To not halt the main clock Set to 0 To halt the main clock Set to 1 Operation in subclock mode Halt sub clock oscillation in subclock on RC oscillation mode bit OSCDS2 To not halt the sub clock Set to 0 To halt the sub clock Set to 1 Operatio...

Page 221: ...r 23 Sub Oscillation Stabilisation Timer Page No 299 for details When the main clock oscillation is halted OSCDS1 1 or the sub clock oscillation is halted OSCDS2 1 an oscillation stabilization wait time for main clock or subclock is also required if a reset INIT occurs that switches the clock source to the main clock In this case operation after the reset is not guaranteed if the wait time set in ...

Page 222: ...206 Chapter 13 Clock Control 8 Caution ...

Page 223: ... in the range of 1 64 Clock auto gear up down function to prevent voltage drops and surges 3 Frequency calculation CLKB frequency is determined by f CLKB Main Osc PLLDIVM_DVM 1 PLLDIVN_DVN 1 PLLDIVM_DVM 1 DIVR0_B 1 CLKP frequency is determined by f CLKP Main Osc PLLDIVM_DVM 1 PLLDIVN_DVN 1 PLLDIVM_DVM 1 DIVR0_P 1 CLKT frequency is determined by f CLKT Main Osc PLLDIVM_DVM 1 PLLDIVN_DVN 1 PLLDIVM_D...

Page 224: ... 6 etc Note The register value can not be changed once PLL is selected as clock source CLKS 1 0 10 Note It is strongly recommended to disable the PLL CLKR PLL1EN 0 while or after changing the PLLDIVM and PLLDIVN registers and to enable the PLL CLKR PLL1EN 1 afterwards PLLDIVN Address 048Dh Access Byte Halfword Word 7 6 5 4 3 2 1 0 bit DVM3 DVM2 DVM1 DVM0 0 0 0 0 0 0 0 0 Initial value INIT pin inpu...

Page 225: ...ratio 2 4 6 etc Note The register value can not be changed once PLL is selected as clock source CLKS 1 0 10 DVN5 DVN0 Φ Base clock divide by N feedback to PLL 000000 Base clock FCL MAIN 1 no division 000001 Base clock FCL MAIN 2 division by 2 000010 Base clock FCL MAIN 3 division by 3 000011 Base clock FCL MAIN 4 division by 4 000100 Base clock FCL MAIN 5 division by 5 000101 Base clock FCL MAIN 6...

Page 226: ... 0 0 0 0 0 0 0 0 Initial value INIT pin input watchdog reset X X X X X X X X Initial value Software reset R W R W R W R W R W R W R W R W Attribute MLG5 MLG0 Divide by G step multiplier 00000000 Divide by G step x 1 multiply by 1 00000001 Divide by G step x 2 multiply by 2 00000010 Divide by G step x 3 multiply by 3 00000011 Divide by G step x 4 multiply by 4 00000100 Divide by G step x 5 multiply...

Page 227: ...Interrupt Enable Gear UP Bit2 Interrupt Flag Gear UP While switching from clock source oscillator to clock source PLL this flag is set when the divide by G counter reaches the end value defined by the divide by M counter This bit is read as 1 at a Read Modify Write instructions Writing 1 has no effect IEUP Function 0 Gear UP interrupt disabled Initial value 1 Gear UP interrupt enabled GRUP Functio...

Page 228: ...t CK MHz Frequency Parameter Clockgear Parameter PLL Output X MHz Core base Clock MHz DIVM DIVN DIVG MULG 4 2 25 16 24 200 100 4 2 24 16 24 192 96 4 2 23 16 24 184 92 4 2 22 16 24 176 88 4 2 21 16 20 168 84 4 2 20 16 20 160 80 4 2 19 16 20 152 76 4 2 18 16 20 144 72 4 2 17 16 16 136 68 4 2 16 16 16 128 64 4 2 15 16 16 120 60 4 2 14 16 16 112 56 4 2 13 16 12 104 52 4 2 12 16 12 96 48 4 2 11 16 12 8...

Page 229: ...requencies to slower ones when gearing down The frequency steps are performed in multiple of the PLL output frequency e g the setting of Oscillator 4 MHz M 2 N 20 which is a frequency multiplication of M N 40 with PLL output 160 MHz and frequency output to C Unit 80 MHz The gear divider can be set to any even divider in this example it is G 20 which causes the following gear up when switching from...

Page 230: ...ed arithmetic series of the first sum term with i G j G M mul MULG t 1 f pllout For the above given setting this equals 1483 PLL output clock cycles with a duration from the start fre quency to the target frequency of 9262500 ps about 9 3 us duration mul t i i 1 i 2 6 k i k 1 k j 1 i ...

Page 231: ...r gearing up or down also enable the corresponding interrupt enables PLLCTRL IEUP PLLCTRL IEDN Wait for the PLL stabilization time Set the base clock division registers DIV0R DIV1R Switch the clock source to the PLL CLKR CLKS 00 10 Wait for the PLLCTRL GRUP gear up flag either by polling or by interrupt before switching the clock source back to oscillation or confirm the setting of PLLCTRL GRUP 1 ...

Page 232: ...216 Chapter 14 PLL Interface 7 Caution ...

Page 233: ...clock for the CAN is not influenced by the clock modulation If the CLKCAN source is set core clock CLKB then the clock for the CAN is also modulated if the clock modulator is enabled 2 Features CAN clock source selectable out of Main Oscillation Base Clock CLKB and PLL output Free programmable divide by C counter in the range of 1 16 Individual clock disable function for each CAN controller X FB C...

Page 234: ...y C counter it is not recommended The resulting output clock will have an odd clock duty ratio direct PLL output can have up to 90 10 duty Always select at least a division ratio 1 CANCKD Address 04C1h Access Byte 7 6 5 4 3 2 1 0 bit CPCKS1 CPCKS0 DVC3 DVC2 DVC1 DVC0 0 0 0 0 0 0 0 0 Initial value INIT pin input watchdog reset 0 0 X X X X X X Initial value Software reset R0 W0 R0 W0 R W R W R W R W...

Page 235: ...are reset R W0 R W0 R W R W R W R W R W R W Attribute CANCKD5 CANCKD0 Function 0 CAN controller 0 is enabled 1 CAN controller 0 is disabled 0 CAN controller 1 is enabled 1 CAN controller 1 is disabled 0 CAN controller 2 is enabled 1 CAN controller 2 is disabled 0 CAN controller 3 is enabled 1 CAN controller 3 is disabled 0 CAN controller 4 is enabled 1 CAN controller 4 is disabled 0 CAN controller...

Page 236: ...220 Chapter 15 CAN Clock Prescaler 3 Registers ...

Page 237: ...r sub clock the MCU is reset and the reset cause can be checked after reset vector fetch If the sub clock is failing while the MCU is in main clock mode reset can be delayed until the transition to sub clock mode or no reset will be initiated The user can choose the behaviour with a control bit in the Clock Supervisor Control Register There are two independent supervisors one for the main clock an...

Page 238: ...k to sub clock modes if sub clock is already missing 1 perform reset upon transition from main clock to sub clock modes if sub clock is already missing bit2 SSVE Sub clock supervisor enable 0 disable sub clock supervisor 1 enable sub clock supervisor bit3 MSVE Main clock supervisor enable 0 disable main clock supervisor 1 enable main clock supervisor bit4 RCE RC oscillator enable 0 disable RC osci...

Page 239: ...C oscillator Do not disable the RC oscillator by setting this bit to 0 while the main or sub clock supervisors are still enabled First the supervisors must be disabled then it must be checked that MM and SM are 0 then RCE can be set to 0 If either MM or SM bits are 1 RCE must not be set to 0 This bit is set to 1 by Power On reset or external reset Other types of reset will not affect this bit 3 MS...

Page 240: ...ed to device specific outputs see the datasheet of the used device for the infor mation which pins are used by setting OUTE 1 Internal Bus Clock Supervisor Main Clock Supervisor MCLK EN STBY RC_CLK NO_MCLK Sub Clock Supervisor SCLK EN STBY RC_CLK NO_SCLK Control Logic NO_MCLK NO_SCLK SCLK_STBY SSEN MCLK_STBY MSEN 0 1 S 0 1 S RC_CLK RC_CLK RC_CLK Clock Supervisor Control Register CSVCR CLK RC_CLK 0...

Page 241: ...his case is a safe state The user must make sure with external pull up pull down resistors that all relevant signal are pulled to the correct level The sub clock supervisor is enabled after the completion of the sub clock timeout TO_SCLK from the timeout counter The timeout counter is clocked with RC oscillation clock If the main clock stops while the main clock supervisor is enabled the main cloc...

Page 242: ...Modes Figure 4 1 Timing Diagram Initial settings main clock missing during power on reset PONR MCLK SCLK RC_CLK OSC_STAB MSVE MSEN SSVE SSEN MCLK_STBY SCLK_STBY TO_MCLK TO_SCLK EXT_RST EXT_RST_OUT MCLK_OUT SCLK_OUT MCLK_MISSING SCLK_MISSING SRST ...

Page 243: ...re 4 2 Timing Diagram Initial settings main clock missing during oscillation stabilisation wait time PONR MCLK SCLK RC_CLK OSC_STAB MSVE MSEN SSVE SSEN MCLK_STBY SCLK_STBY TO_MCLK TO_SCLK EXT_RST EXT_RST_OUT MCLK_OUT SCLK_OUT MCLK_MISSING SCLK_MISSING SRST ...

Page 244: ...re 4 3 Timing Diagram Initial settings main clock missing after oscillation stabilisation wait time PONR MCLK SCLK RC_CLK OSC_STAB MSVE MSEN SSVE SSEN MCLK_STBY SCLK_STBY TO_MCLK TO_SCLK EXT_RST EXT_RST_OUT MCLK_OUT SCLK_OUT MCLK_MISSING SCLK_MISSING SRST ...

Page 245: ...ion Modes Figure 4 4 Timing Diagram Initial settings sub clock missing before timeout PONR MCLK SCLK RC_CLK OSC_STAB MSVE MSEN SSVE SSEN MCLK_STBY SCLK_STBY TO_MCLK TO_SCLK EXT_RST EXT_RST_OUT MCLK_OUT SCLK_OUT MCLK_MISSING SCLK_MISSING SRST ...

Page 246: ...tion Modes Figure 4 5 Timing Diagram Initial settings sub clock missing after timeout PONR MCLK SCLK RC_CLK OSC_STAB MSVE MSEN SSVE SSEN MCLK_STBY SCLK_STBY TO_MCLK TO_SCLK EXT_RST EXT_RST_OUT MCLK_OUT SCLK_OUT MCLK_MISSING SCLK_MISSING SRST ...

Page 247: ...lock or sub clock supervisor is still enabled Then check that both SM and MM bit 5 and bit 6 of CSVCR are still 0 Disable the RC oscillator by setting RCE to 0 If either SM or MM bit is 1 RCE must not be set to 0 The main clock supervisor is disabled by setting MSVE bit 3 of CSVCR to 0 The sub clock supervisor is disabled by setting SSVE bit 2 of CVSVR to 0 Figure 4 6 Timing Diagram Disabling the ...

Page 248: ... must only take place 100 s after the RC oscillator is enabled The software has to take care that this time constraint is met The sub clock supervisor is enabled by setting SSVE bit 2 of CSVCR to 1 Enabling of the sub clock supervisor must only take place 100 s after the RC oscillator is enabled The software has to take care that this time constraint is met Figure 4 7 Timing Diagram Re enabling th...

Page 249: ...ck has stopped in main clock mode and this was detected by the sub clock supervisor the behaviour upon transition to sub clock mode depends on the state of the SRST bit If SRST is set to 0 initial value reset is not asserted at the transition to sub clock mode The transition is performed using the RC oscillation clock as sub clock In this case it is recommended to check the SM bit before the trans...

Page 250: ... Figure 4 9 Timing Diagram Sub clock missing in main clock mode SRST 1 PONR MCLK SCLK RC_CLK OSC_STAB MSVE MSEN SSVE SSEN MCLK_STBY SCLK_STBY TO_MCLK TO_SCLK EXT_RST EXT_RST_OUT MCLK_OUT SCLK_OUT MCLK_MISSING SCLK_MISSING SRST Clock Mode Main Main Sub ...

Page 251: ... Modes Figure 4 10 Timing Diagram Waking up from sub clock mode PONR MCLK SCLK RC_CLK OSC_STAB MSVE MSEN SSVE SSEN MCLK_STBY SCLK_STBY TO_MCLK TO_SCLK EXT_RST EXT_RST_OUT MCLK_OUT SCLK_OUT MCLK_MISSING SCLK_MISSING SRST Main Sub Main Clock Mode ...

Page 252: ...led immediately after wake up from stop mode The main clock supervisor is enabled after the oscillation stabilisation wait time with the rising edge of the signal OSC_STAB or in case the main clock is missing after wake up from stop mode after the main clock timeout TO_MCLK from the timeout counter The timeout counter is clocked with RC oscillation clock The sub clock supervisor is enabled after t...

Page 253: ...ust be 0 initial value Before the transition to sub clock mode it has to be confirmed by software that the sub clock has been substituted by the RC oscillation clock This can be accomplished by checking that SM bit bit 5 of CSVCR is 1 and RCE bit bit 4 of CSVCR is 1 Figure 4 12 Timing Diagram Sub clock mode with single clock device PONR MCLK SCLK RC_CLK OSC_STAB MSVE MSEN SSVE SSEN MCLK_STBY SCLK_...

Page 254: ...must check the reset cause by reading the WDTC register at address A8H If ERST bit 4 of WDTC is set the cause was either external reset at the RSTX pin or the clock supervisor If neither SM bit nor MM bit bit 5 and bit 6 of CSVCR is set reset cause was the external reset If SM is 1 the reset cause is a missing sub clock and if MM is 1 the reset cause is a missing main clock ...

Page 255: ... Figure 1 1 Frequency spectrum of the modulated clock fundamentals only Modulation degree and frequency resolution in frequency modulation mode Maximum and minimum frequencies Fmax and Fmin of the modulated clock are defined by the modulation degree parameter Furthermore the resolution of the modulation range is selectable in 7 steps from low 1 to high 7 Higher resolution implies a finer granulari...

Page 256: ...k modulator registers Figure 2 1 Clock modulator registers Initial value 1 1 1 1 1 1 0 1B R W R W R W R W R W R W R W R W Address H 0004B9 CMPRL lower Initial value X X 0 0 0 0 0 1 0B CMPRH upper H 0004B8 15 14 13 12 11 10 9 8 Initial value X 0 0 1 0 X 0 0B R W R W R W R R W R W H 0004BB CMCR 1 0 3 2 5 4 7 6 1 0 3 2 5 4 7 6 Re served Re served Re served FMOD FMODPDX R W R W R W R W R W R W RUN ...

Page 257: ...modulation mode needs some additional configuration CMPR register bit 0 PDX Power down bit 0 power down mode 1 power up bit 1 FMOD Frequency modulation enable bit 0 Frequency modulation mode disabled 1 Frequency modulation mode enabled bit 3 FMOD RUN Modulator status in frequency modulation mode 0 Clock frequency unmodulated 1 Clock frequency modulated R W Readable and writable R Read only X Undef...

Page 258: ...n mode by setting FMOD to 1 the modulator is calibrated During this time the clock is unmodulated Therefore it takes several us before the output clock switches to modulated clock and the FMODRUN bit is set to 1 The calibration time depends on the frequency of the oscillator At oscillator Fc 4MHz Calibration time 64 00us calibration time 256 Fc During normal operation after calibration is finished...

Page 259: ...e parameter register CMPR After enabling the frequency modulation mode by setting FMOD to 1 the modulator is calibrated During this time the clock is unmodulated Therefore the output clock does not switch immediately to modulated clock The status of the clock frequency modulated unmodulated is indicated by the FMODRUN status bit Please refer to the FMODRUN bit description Due to the synchronizatio...

Page 260: ...ttings The modulation parameter affects only the frequency modulation mode Note The modulation parameter must be changed only when the modulator is disabled and the RUN flag is 0 FMOD 0 FMODRUN 0 Modulation parameter register contents modulator enabled in frequency modulation mode modulator is calibrating modulation not active 1 1 0 modulator is running in frequency modulation mode modulation is a...

Page 261: ... 0 Modulation Parameter bits Depending on the PLL frequency the following modulation parameter settings are possible The corresponding CMPR register value is stated in the most right column Table 2 3 Function of each bit of the modulation parameter register CMPR Bit name Function ...

Page 262: ...ency modulated clock Fmax maximal frequency occurring in the frequency modulated clock phase skew The maximal phase shift of the modulated clock relative to the unmodulated reference clock in terms of clock periods of the unmodulated clock Example phase skew 1 44 In worst case a sequence of n periods of the modulated clock can be 1 44 T0 shorter or 1 44 T0 longer than a sequence of n periods of th...

Page 263: ...ing depends much on the actual application the whole system and the requirements In order to find the optimal modulation parameter setting in frequency modulation mode the following approach is Table 2 4 Modulation Parameter settings F0 MHz resolution mod degree Fmin MHz Fmax MHz phase skew 50 periods phase skew min max periods CMPR start 1 Switch modulator from power down to power up mode PDX 1 2...

Page 264: ...0x05F2 Fmax 30 34 MHz 4 perform EMI measurements 5 if the EMI measurements does not fulfill the requirements you may either reduce the modulation degree at the same frequency resolution this may improve the reduction in the upper frequency band 100 MHz but decrease the reduction of the fundamental 100 MHz e g resolution 7 degree 1 CMPR 0x03F9 or increase the modulation degree at a lower frequency ...

Page 265: ...ization wait using the timebase counter Wait time after a settings initialization Invoked automatically timebase counter INIT Initial oscillation stabilization wait after pin input Watchdog reset If the main clock oscillation has not been halted Oscillation stabilization wait not required If the main clock oscillation has halted Oscillation stabilization wait is required Example If a watchdog rese...

Page 266: ...rate this time is recommended A wait time is required after the main PLL operation is enabled A wait time is required after the main PLL multiplier setting is changed 3 Configuration Figure 3 1 Configuration Diagram Figure 3 2 Register List Time base counter when used to generate the oscillation stabilization wait CLKR bit 1 0 F 0 0 1 1 0 1 1 0 F CL SUB 2 2 CL MAIN F F CL SUB 2 CL MAIN CKS1 CKS0 B...

Page 267: ...d Bit3 2 Oscillation stabilization time selection F2 Main clock divided by two or subclock In the case of a reset triggered by an INIT pin input operation defaults to 00 F2 x 21 main clock In the case of other resets or on recovering from stop mode the specified clock main or sub and oscillation stabilization wait time OS 1 0 are used The count is performed by the timebase counter Bit1 Sub clock o...

Page 268: ...y not be modified Example To select the subclock after an INIT reset first write 01B and then write 11B subclock The clock source for the timebase counter during the oscillation stabilization wait time is set by the clock source selection bits 7 6 5 4 3 2 1 0 bit SCKEN PLL1EN CLKS1 CLKS0 X X X X 0 0 0 0 Initial value INIT pin input X X X X X X X X Initial value Software reset R W0 R W0 R W0 R W0 R...

Page 269: ...lation stabilization wait time provided by timebase timer counter Initial value minimum value If the INITX pin input 4 is not maintained the wait time is too short 7 Operation initialization reset reset cancellation sequence 8 Main RUN INIT Pin input when main clock running The device goes to the operation initialization reset RST state automatically after the minimum oscillation stabilization wai...

Page 270: ...peration initialization SRST 8 Operation initialization reset sequence 9 Main RUN Note If a watchdog reset occurs when the main clock oscillation is halted during subclock mode subclock is being used as clock source by the main clock oscillation halt bit OSCCR OSCDS1 the device changes to the oscillation stabilization wait state after the settings initialization reset INIT is released The device t...

Page 271: ...d stop mode 2 The timebase counter is cleared automatically and then starts counting 3 Oscillation stabilization wait time specified value Set the interval time beforehand to provide an adequate oscillation stabilization wait time 4 Interval time for timebase counter 5 Main PLL operation 5 000h Using the time base timer to wait main PLL lock Example main PLL startup 13 2 Time base counter count 1 ...

Page 272: ...d Using the timebase timer interrupt is recommended However the main PLL must not be selected as the clock source See Chapter 19 Timebase Timer Page No 263 for details 5 5 Generating an Oscillation Stabilization Wait when Changing from Subclock Mode to Main Clock Mode When main clock continues to run during subclock mode If not using main PLL after changing clock No oscillation stabilization wait ...

Page 273: ...ovides the stabilization time required by the oscillation circuit INIT pin input after power turned on INIT pin input when oscillation halted during stop mode INIT pin input when subclock selected as clock source and main clock oscillation halted Timebase timer Using the timebase timer to generate the main PLL lock time is recommended See Chapter 20 Software Watchdog Timer Page No 273 for details ...

Page 274: ...258 Chapter 18 Timebase Counter 5 Operation 5 8 Whether or not a Stabilization Wait is Required for Each State Transition See figure below ...

Page 275: ...ings required to specify the PLL lock wait time See Chapter 19 Timebase Timer Page No 263 Table 6 1 Settings Required to Specify the Oscillation Stabilization Wait Time Setting Setting register Setting procedure Oscillation stabilization wait time setting Standby control register STCR See 7 1 Table 6 2 Settings Required to Setup an INITX Pin Reset Setting Setting item Setting procedure INITX pin i...

Page 276: ... is not initialized except by a settings initialization triggered by the external INIT pin Scenario Oscillation stabilization wait time selection bits OS 1 0 Example oscillation stabilization wait time after a reset INIT or on recovering from stop mode Oscillation stabiliza tion wait time 4 0MHz Main clock running 32 768kHz Subclock running To not halt the main PLL or oscillator during stop mode N...

Page 277: ...ion wait minimum value is too short the width of the INIT pin must be sufficient to provide the stabilization time Subclock operation main clock halted O Sub sleep sub stop main clock halted O Main clock oscillation stabilization wait O State before transition Oscillation Main clock oscillation enabled Is oscillation stabilization wait required To set the oscillation stabilization wait time PLL Ma...

Page 278: ...n the following three cases maintain the INIT pin input at the L level for long enough to provide the oscillation stabilization wait time required by the oscillation circuit INIT pin input after turning on the power INIT pin input after oscillation halted in stop mode INIT pin input when subclock selected as the clock source and main clock oscillation halted Accordingly to stabilize the oscillatio...

Page 279: ...mer TBT Type Detects timebase timer bit output and generates an interval interrupt Quantity 1 Interval time 8 types Timebase timer bit output Period 211 FF 212 FF 213 FF 222 FF 223 FF 224 FF 225 FF 226 FF Operation start stop Always in operation Can be replaced by interrupt request enable control Timebase counter clear Continuously writes A5 5A in the timebase counter clear register CTBR using the...

Page 280: ...equest With interrupt request WRITE 0 Flag clear Selector Edge detection 21 22 23 24 210 211 212 213 214 215 216 217 218 219 220 221 222 223 0 1 2 3 224 225 226 TBC2 TBC0 TBCR bit 5 3 211 0 0 1 1 0 1 1 0 212 213 222 223 0 0 1 1 0 1 1 0 224 225 226 1 0 1 0 1 1 1 1 Timebase timer Timebase timer 0 TBIE Interrupt disable Interrupt enable CTBR Clears the counter after writing A5h and then 5Ah TBIF 9 10...

Page 281: ... the stop caused by an interrupt Bit2 Reserved bit Writing does not affect the operation The read value is indefinite 7 6 5 4 3 2 1 0 bit TBIF TBIE TBC2 TBC1 TBC0 SYNCR SYNCS 0 0 X X X X 0 0 Initial value INIT terminal input watchdog reset 0 0 X X X X X X Initial value the software reset R RM1 W R W R W R W R W RX WX RX WX R W Attribute TBIF Operation Read Write 0 With no interrupt request Flag is...

Page 282: ...immediately after writing 5AH All bits are 0 There is no time restrictions between A5H and 5AH but if A5H is written followed by the one other than 5AH you should write A5H again If not the timebase counter cannot be cleared even if 5AH is written The read value is indefinite Clearing the timebase counter using the timebase counter clear register temporarily modifies the relevant items shown below...

Page 283: ...ware 7 Setting the timebase timer interrupt request enable bit to 1 8 The main PLL locks 9 A timebase timer interrupt occurs when the timebase timer interval time has elapsed 10 Setting the main PLL to the operation clock 3 Time 000h Example of the Main PLL oscillation 2 Clock switching CLKS 1 0 Main PLL lock wait by the timebase timer 211 4 6 CTBR 00 10 5 A5 Main PLL enable PLL1EN Timebase timer ...

Page 284: ...er control register TBCR Refer to 7 1 Timebase counter clear Timebase counter clear register CTBR Refer to 7 5 Table 6 2 Setting Required for Interrupting the Timebase Timer Setting Setting register Setting method Setting the timebase timer interrupt vector and interrupt level Refer to Chapter 24 Interrupt Control Page No 311 Refer to 7 6 Setting the main clock oscillation stability wait timer int...

Page 285: ... Page No 271 7 6 How about the interrupt associated registers Setting timebase timer s interrupt vector and interrupt level The relationship between the interrupt level and vector is shown in the following table Refer to Chapter 24 Interrupt Control Page No 311 for more information on the interrupt level and interrupt vector The interrupt request flag TBCR TBIF cannot automatically be cleared As a...

Page 286: ... unnecessary 7 8 How is an interrupt enabled Interrupt request enable and interrupt request flag Setting interrupt enable is conducted using the interrupt request enable bit TBCR TBIE Clearing the interrupt request is performed using the interrupt request bit TBCR TBIF Interrupt request enable bit TBIE Interrupt disable Set the value to 0 Interrupt enable Set the value to 1 Interrupt request bit T...

Page 287: ...ter using a program If you write data in the timebase counter clear register CTBR in the order of A5H and 5AH the timebase counter is cleared immediately after writing 5AH All bits are 0 Although there are no restrictions on the write timings for A5H and 5AH writing A5H followed by a one other than 5AH the clearing operation is not performed if A5H is not written again even if 5AH is written If th...

Page 288: ...272 Chapter 19 Timebase Timer 8 Caution ...

Page 289: ...r Quantity 1 Count clock interval time Bit output from the timebase timer 4 types 220 FF 222 FF 224 FF 226 FF Can be set only once after the reset RST Clearing 1 bit counter Successively writes A5 5A to watchdog reset generation delay register WPR by the software Operation start stop This timer starts to operate once it writes data to the watchdog control register RSRR for the first time after the...

Page 290: ...23 24 25 Selector Edge detection WIF OSCR bit 7 0 1 Without interrupt request With interrupt request WRITE 0 Flag clear 1 bit counter WT1 WT0 220 0 0 1 1 0 1 1 0 222 224 226 WPR To the reset circuit Watchdog timer Sleep Stop Oscillation stability wait RUN 26 bit counter CTBR Clears the counter after writing A5h and then 5Ah Clears the counter after writing A5h and then 5Ah WIF 0 1 For watchdog det...

Page 291: ... INIT was triggered by the watchdog timer The watchdog reset occurred flag WDOG is cleared to 0 after reading Bit4 External reset occurred flag Indicates whether a reset RST was triggered by the RST pin input The external reset occurred flag ERST is cleared to 0 after reading Bit3 Software reset occurred flag Indicates whether a software reset has been triggered by writing to the software reset bi...

Page 292: ...lection bit can be read to know the set value Note For more information on bits used for timers other than the watchdog timer refer to Chapter 9 Reset Page No 139 1 RST has been triggered by a software reset LINIT Meaning 0 No INIT has been triggered by the low voltage detection 1 INIT has been triggered by the low voltage detection WT1 WT0 The minimum writing interval required for WPR so that the...

Page 293: ... written again If not writing 5AH does not set the 1 bit counter to 0 The read value is indefinite Both A5H and 5AH must be written within the specified interval as shown below to prevent the watchdog reset from being generated The intervals are shown in the following table according to the watchdog interval time selection bit RSRR WT 1 0 4 3 CTBR Timebase Counter Clear Register This register is u...

Page 294: ...gister with A5 and 5A has been performed Watchdog timer clears 8 Interval signal output from the timebase counter The watchdog timer counts 9 MCU runs away the runaway of MCU is assumed 10 Within interval time by software writing to the WPR register with A5 and 5A has not been performed 11 Interval signal output from the timebase counter The watchdog timer counts 12 Runaway is detected WODOG flag ...

Page 295: ... 5 5 Temporarily Stopped Watchdog Timer Automatic Generation Postponement The watchdog timer resets the 1 bit counter used for detecting the watchdog reset to 0 as initialization while CPU program operation is stopped In this state the generation of the watchdog reset is postponed The states where programs stop running are concretely shown below Sleep Stop Oscillation stability wait RUN Is in brea...

Page 296: ...g method Interval time setting Watchdog timer control register RSRR Refer to 7 1 Startup of the watchdog Refer to 7 2 Table 6 2 Setting Required for Delaying the Generation of the Watchdog Setting Setting register Setting method Setting required for delay the generation of the watchdog reset Watchdog reset generation delay register WPR Refer to 7 3 Table 6 3 Setting Required for Checking the Gener...

Page 297: ...OG is set to 1 the watchdog reset has been generated 7 4 How is the watchdog stopped The watchdog cannot be stopped by the software The watchdog can be stopped only with the reset INIT pin input watchdog reset 7 5 How do I clear the watchdog timer 1 bit counter Successively writing A5H and 5AH in the watchdog reset generation postponement register WPR causes the 1 bit counter used for detecting th...

Page 298: ...RST and LINIT is set to 0 when it is read The watchdog reset holds the oscillation stability wait time Refer to Chapter 18 Timebase Counter Page No 249 The watchdog reset from the main RUN or the sub RUN where the main clock oscillation is in process cannot have the oscillation stability wait time because the main clock is oscillating Refer to Chapter 19 Timebase Timer Page No 263 for the method o...

Page 299: ...nter is not cleared within the postponement duration e g due to infinite loop in the application this module provides a reset signal initialisation reset INIT which width is typical 20us 2 RC clock cycles at typical 100kHz If the CPU is in a standby mode as described below this watchdog timer stops SLEEP mode the CPU stops the peripherals run STOP mode the CPU and the peripherals stop RTC mode the...

Page 300: ...eeds to be cleared periodically after releasing the reset Hardware watchdog timer control status register This register has the reset flag and clear bit for the counter Occuring of the watchdog reset If the counter has not been cleared periodically this module provides a setting initialization reset INIT The width of internal reset signal is 63 times the system base clock After the watchdog reset ...

Page 301: ...always read as 1 Bit2 1 Reserved bits Always write 0 to these bits Bit0 CPUF CPU reset Flag This bit is initialized by external reset input INITX or clock supervisor reset but not by internal reset Writing 0 clears this bit writing 1 has no effect 7 6 5 4 3 2 1 0 bit RESV0 RESV0 RESV0 RESV1 CL RESV0 RESV0 CPUF 0 0 0 1 1 0 0 0 Initial value INIT pin input watchdog reset 0 0 0 1 1 0 0 X Initial valu...

Page 302: ...ed bits Always write 0 to these bits Bit1 0 ED Elongate watchdog duration This setting is not available on MB91V460 7 6 5 4 3 2 1 0 bit ED1 ED0 0 0 Initial value INIT pin input watchdog reset 0 0 Initial value Software reset RX W0 RX W0 RX W0 RX W0 RX W0 RX W0 R W R W Attribute ED1 0 Function 00 The watchdog period is 2 16 RC clock cycles initial setting 01 The watchdog period is 2 17 RC clock cyc...

Page 303: ... is not cleared periodically setting initialization INIT reset occurs Period of the hardware watchdog timer The timer width is 16 bit Since the RC oscillator is used as clock source of the hardware watchdog timer the duration of the timer deviates with the RC oscillator accuracy Note The watchdog duration elongation ED1 0 setting is not available on MB91V460 In that case ED1 0 is always 00 ED1 0 M...

Page 304: ... is set to 0 there is no minimum writing limitation the timer is cleared and the occurrance of reset is postponed Just writing to the register without setting CL to 0 does not clear the timer Timer stop and clear In modes where the CPU does not work SLEEP STOP or RTC mode the timer is cleared first then the counting is stopped During DMA transfer During DMA transfer between D bus modules the writi...

Page 305: ...s been stopped OSCCR OSCDS1 1 while the subclock is being operated In addition this timer is best suited for interval timers or system clocks for real time OS 2 Features Type 23 bit free run counter Quantity 1 Clock source Main clock source oscillation Period 1 FCL MAIN Interval time 3 types Period 212 FCL MAIN 217 FCL MAIN 223 FCL MAIN 1 0ms 32 7ms 2s main clock 4MHz Cause of timer clear Software...

Page 306: ...mer operation enable WEN OSCR bit 5 0 1 Operation stop Operation enable Interrupt disable Interrupt enable WIE OSCR bit 6 0 1 Selector Edge detection WIF OSCR bit 7 0 1 Without interrupt request With interrupt request WRITE READ 0 1 Flag clear Not affected 1 0 Main clock Oscillation stability wait interrupt 46 Main clock Source oscillation 23 bit free run timer 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1...

Page 307: ...Be sure to write 0 The read value is 0 Bit2 1 Interval period selection The reset does not initialize Be sure to set it after the startup Bit0 Timer clear The timer is also cleared by INITX terminal input and watchdog reset Refer to 8 Caution Page No 297 7 6 5 4 3 2 1 0 bit WIF WIE WEN WS1 WS0 WCL 0 0 0 X X 0 0 1 Initial value INIT terminal input watchdog reset X X X X X X X X Initial value Softwa...

Page 308: ...ount enable WEN 1 by the software 5 Releases main clock stop OSCCR OSCDS1 0 while the subclock is in operation by the software and starts main clock oscillation 6 Starts counting The timer counts up using the main clock source oscillation 7 Stabilizes the main clock oscillation 8 The selected interval time is used Detects the falling edge of the dividing 217 9 Generates a main clock oscillation st...

Page 309: ... Clears the timer WCL 0 clears flags WIF 0 enables interrupt request WIE 1 enables timer count WEN 1 by the software 3 The timer counts up using the main clock source oscillation 4 Generates interval interrupt at the selected interval time Falling of the dividing 217 5 Processing caused by an interrupt Software Clears interrupt request WIF 0 6 Repeats Items 3 to 5 ...

Page 310: ...tings Required for Enabling the Main Clock Oscillation Stability Wait Timer Interrupt Setting Setting register Setting method Sets the main clock oscillation stability wait timer interrupt vector and Sets free run timer interrupt level Refer to Chapter 24 Interrupt Con trol Page No 311 7 5 Sets the main clock oscillation stability wait timer interrupt Clears interrupt request Enables interrupt req...

Page 311: ...set to 000000 H 7 5 What happens with the interrupt associated registers Setting the interrupt vector and interrupt level of the main clock oscillation stability wait timer The relationship between the interrupt level and the interrupt vector is shown in the following table Refer to Chapter 24 Interrupt Control Page No 311 for the interrupt level and interrupt vector As the interrupt request flag ...

Page 312: ...quest enable bit OSCRH WIE Clearing an interrupt request is performed with the interrupt request bit OSCRH WIF 7 8 How is the main clock oscillation stability wait timer stopped counting Sets with the timer operation enable bit OSCRH WEN Refer to 7 3 In addition if the MCU stops the main clock while the subclock is being operated the main clock oscillation stability wait timer also stops counting ...

Page 313: ... wait timer is counted up with the main clock As a result in the following state the counting of the timer used to stop the main clock oscillation also stops If the timer operation enable bit OSCRH WEN is 0 the timer stops counting If the main clock is stopped in the stop mode STCR OSCD1 1 the timer stops counting from the moment the stop mode is activated If the main clock oscillation is stopped ...

Page 314: ...298 Chapter 22 Main Oscillation Stabilisation Timer 8 Caution ...

Page 315: ...he main clock is in operation This timer is can be used for acquiring sub clock oscillation stability wait time to resume sub clock oscillation after the sub clock oscillation has been stopped OSCCR OSCDS2 1 while the RC oscillator is being operated 2 Features Type 15 bit free run counter Quantity 1 Clock source Subclock source oscillation Period 1 FCL SUB 1 32 768kHz Interval time 4 types Period ...

Page 316: ... free run timer Sub clock Source oscillation 32 768 kHz WCL WPCR bit 2 0 1 Timer clear Does not affect the operation Timer clear 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 21 22 23 24 25 26 27 28 29 210 211 212 213 214 215 Selector Edge detection WS1 0 WPCR bit 2 1 0 0 0 Interval time CL SUB CL SUB CL SUB CL SUB 210 F 213 F 214 F 215 F WIE WPCR bit 6 0 1 Interrupt disable Interrupt enable Clock timer Inte...

Page 317: ...WIE is set to 1 an interrupt request is immediately generated Bit5 Timer operation enable Bit4 3 Reserved bit Be sure to write 0 The read value is 0 Bit2 1 Interval period selection Bit0 Timer clear The timer is also cleared by INITX terminal input and watchdog reset Notes 1 Initial value can be set using the setting initialization reset INIT terminal input 7 6 5 4 3 2 1 0 bit WIF WIE WEN WS1 WS0 ...

Page 318: ... initialization reset Software reset holds the current value instead of initializing it 2 If you set the interrupt request enable WIE 1 and the interval period selection WS 1 0 after canceling the reset be sure to simultaneously set the timer interrupt request flag WIF and the timer clear WCL 0 ...

Page 319: ... 5 The subclock oscillation starts 6 Counts up with the subclock source oscillation 7 Make the subclock oscillation stable 8 Makes the interval time be the selected time Detects the falling of 210dividing 9 If the flag WIF becomes 1 the subclock oscillation stability wait interrupt request is generated 10 Processing cause by an interrupt Software Switching the operation clock Sub RUN main RUN 11 I...

Page 320: ...ware 3 The timer counts up with the subclock Source oscillation 4 Makes the interval time be the selected time Detects the fall of 213 5 If the flag WIF is set to 1 interval interrupt request Clock interrupt request is generated 6 Processing caused by an interrupt Software The interrupt request clear WIF 0 Arbitrary processing such as clock counting 7 Repeats Items 3 to 6 WIF Clock timer counting ...

Page 321: ...er interrupt enable WIE 1 by the software 5 Switches the MCU operation from the main RUN to sub RUN 6 Switches to the stop mode 7 Makes the interval time be the selected time 0 5 second 8 The interrupt request flag WIF is set to 1 9 As the interrupt request is enabled WIE 1 returns from the stop mode to sub RUN 10 Clears the interrupt request flag by software Writes 0 to the WIF 11 Repeats Items 6...

Page 322: ...bilisation timer control register WPCRH Refer to 7 1 Count clear Refer to 7 4 Table 6 2 Items Required for Enabling the Sub oscillation stabilisation timer Interrupt Setting Setting register Setting method Setting the interrupt vector and the free run timer level of the sub oscillation stabilisation timer Refer to Chapter 24 Interrupt Control Page No 311 Refer to 7 5 Setting the sub oscillation st...

Page 323: ...he sub oscillation stabilisation timer The relationship between the interrupt level and the vector is shown in the following table Refer to Chapter 24 Interrupt Control Page No 311 for more information on the interrupt level and the interrupt vector As the interrupt request flag WPCRH WIF is not automatically cleared clear it before returning from the interrupt processing by the software Writes 0 ...

Page 324: ...errupt request bit WPCRH WIF 7 7 How is the sub oscillation stabilisation timer stopped counting Sets with the timer operation enable bit WPCRH WEN Refer to 7 3 In addition if the MCU stops the sub clock while the mainclock is being operated the sub clock oscillation stability wait timer also stops counting Interrupt request enable bit WIE Interrupt disable Set the value to 0 Interrupt enable Set ...

Page 325: ...ock is made to oscillate starting from subclock stopped state and if the MCU operation mode is switched from the main RUN to the sub RUN mode without waiting until the subclock oscillation becomes stable Be sure to acquire the subclock oscillation stability wait time using the sub oscillation stabilisation timer etc If the main clock is selected as the clock source the oscillation stability wait t...

Page 326: ...310 Chapter 23 Sub Oscillation Stabilisation Timer 8 Caution ...

Page 327: ... from stop mode by a valid interrupt Wakeup Interrupt level Reserved for System level 0 to 14 MNI level 15 Interrupt level 16 to 31 Interrupt disable level 32 As the interrupt level goes up the number goes down Number of interrupt triggers NMI 1 Interrupt from peripheral functions 128 Delayed interrupt 1 Reserved for system for REALOS 2 INT instruction 111 Interrupt priority judging circuit Interr...

Page 328: ... 4 A D 2 Real time clock 1 Main clock oscillation stabilization timer 1 Clock timer 1 Up down counter 2 PPG 3 Free run Timer 2 Input capture 2 Output compare 4 Delayed interrupt 1 Reserved for system REALOS 2 INT instruction 176 Interrupt cause Interrupt request flag Interrupt request enable bit Timebase timer 1 0 SSP 0 Interrupt control CPU side Interrupt level ICRxx ICR 4 0 Interrupt number Prio...

Page 329: ...load Timer 6 Address 044BH Access Byte 39 Reload Timer 7 ICR12 40 Free Run Timer 0 Address 044CH Access Byte 41 Free Run Timer 1 ICR13 42 Free Run Timer 2 Address 044DH Access Byte 43 Free Run Timer 3 ICR14 44 Free Run Timer 4 Address 044EH Access Byte 45 Free Run Timer 5 ICR15 46 Free Run Timer 6 Address 044FH Access Byte 47 Free Run Timer 7 ICR16 48 CAN 0 Address 0450H Access Byte 49 CAN 1 ICR17...

Page 330: ... Output Compare 3 ICR44 104 Output Compare 4 Address 046CH Access Byte 105 Output Compare 5 ICR45 106 Output Compare 6 Address 046DH Access Byte 107 Output Compare 7 ICR46 108 Sound Generator Address 046EH Access Byte 109 Phase Frequ Modulator ICR47 110 System reserved Address 046FH 2 Access Byte 111 System reserved ICR48 112 Prog Pulse Gen 0 Address 0470H Access Byte 113 Prog Pulse Gen 1 ICR49 11...

Page 331: ...d by setting the REALOS compatibility bit addr 0x0C03 IOS 0 ICR61 138 Low Voltage Detection Address 047DH Access Byte 139 SMC Comparator 0 5 ICR62 140 Timebase Overflow Address 047EH Access Byte 141 PLL Clock Gear ICR63 142 DMA Controller Address 047FH Access Byte 143 Main Sub OSC stability wait ...

Page 332: ...specifies the interrupt level of the corresponding interrupt request When the interrupt level set to the interrupt control register is the same as or higher than the level mask value set to the ILM register of the CPU the interrupt request is masked by the CPU side 7 6 5 4 3 2 1 0 bit ICR4 ICR3 ICR2 ICR1 ICR0 1 1 1 1 1 Initial value RX WX RX WX RX WX R WX R W R W R W R W Attribute ICR4 ICR0 bits I...

Page 333: ...r EIT used by system 0 14 00 Address FFFBCh 01 Address FFFB8h 07 Address FFFE0h 63 Address FFF00h 143 Address FFDC0h 32 bits Interrupt number Interrupt level fixed Factor 0 0 Reset vector 1 1 Mode vector 2 4 Reserved for system 5 5 CPU Supervisor Mode 6 6 Memory Protection Exception 7 7 Coprocessor absence trap 8 8 Coprocessor error trap 9 9 INTE instruction 10 10 Instruction break exception 11 11...

Page 334: ...rocessing Interrupt cause generated The interrupt request flag is set to 1 The interrupt request is transmitted to the interrupt control circuit Are interrupt requests enabled The interrupt level and the interrupt number are transmitted to the CPU Is not the corresponding interrupt disabled ICR 31 Which interrupt has the lowest level among the interrupt requests Which interrupt has the lowest numb...

Page 335: ...three settings should be set Set the value 31 to the applicable register in the interrupt control registers ICR00 ICR63 Set the interrupt request enabling bit of the applicable peripheral function to 0 disable Set the interrupt enabling flag I to 0 disable all interrupts Table 6 1 Setting Required to Use Interrupts Setting Setting Registers Setting Procedure Setting the interrupt level Interrupt c...

Page 336: ...the interrupt process They are usually cleared by writing 0 to the bit of the interrupt request flag however there are some exceptions depending on the type of peripheral functions See the chapter for the corresponding peripheral function In C I flag is set to 1 interrupt enable by writing __EI I flag is set to 0 interrupt disable by writing __DI Two underscores ...

Page 337: ...ew External interrupt detects a signal input to an external interrupt input pin and generates an interrupt request 2 Features Quantity 16 INT input 16 channels INT0 INT15 Interrupt levels 4 levels L level H level Rising edge Falling edge Edge detection circuit Pins Interrupt requests ...

Page 338: ...5 DDR24 bit6 DDR24 bit7 0 1 Input only Enable output External interrupt 0 1 2 3 4 5 6 7 External interrupt request level setting bit LB0 LA0 LB1 LA1 LB2 LA2 LB3 LA3 LB4 LA4 LB5 LA5 LB6 LA6 LB7 LA7 External interrupt request bit ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 Enable external interrupt requests EN0 EN1 EN2 EN3 EN4 EN5 EN6 EN7 Interrupt number 16 17 18 19 20 21 22 23 The data direction bit P24 0 P24...

Page 339: ...1 LA11 LB12 LA12 LB13 LA13 LB14 LA14 LB15 LA15 External interrupt request bit ER8 ER9 ER10 ER11 ER12 ER13 ER14 ER15 Enable external interrupt requests EN8 EN9 EN10 EN11 EN12 EN13 EN14 EN15 Interrupt number 24 25 26 27 28 29 30 31 The data direction bit P23 0 P23 2 P23 4 P23 6 P22 0 P22 2 P22 4 P22 6 Pins Port function INT8 INT9 INT10 INT11 RX3 INT12 INT13 INT14 INT15 External interrupt request ena...

Page 340: ...324 Chapter 25 External Interrupt 3 Configuration Figure 3 4 Register List Note See Chapter 24 Interrupt Control Page No 311 about ICR register and interrupt vectors ...

Page 341: ...g bit ERn will be re set to 1 even if the external interrupt request bit ERn is set to 0 Note n 0 to 15 15 14 13 12 11 10 9 8 Bit LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 0 0 0 0 0 0 0 0 Initial value R W R W R W R W R W R W R W R W Attribute 7 6 5 4 3 2 1 0 Bit LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 0 0 0 0 0 0 0 0 Initial value R W R W R W R W R W R W R W R W Attribute 15 14 13 12 11 10 9 8 Bit LB15 LA15 LB14 L...

Page 342: ...bute Symbols Page No 10 An external interrupt request enable bit ENn enables the corresponding external interrupt request Note n 0 to 15 7 6 5 4 3 2 1 0 Bit ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 0 0 0 0 0 0 0 0 Initial value R RM1 W R RM1 W R RM1 W R RM1 W R RM1 W R RM1 W R RM1 W R RM1 W Attribute 7 6 5 4 3 2 1 0 Bit ER15 ER14 ER13 ER12 ER11 ER10 ER9 ER8 0 0 0 0 0 0 0 0 Initial value R RM1 W R RM1 W R R...

Page 343: ... software Remark When waking up from STOP mode with edge detection enabled a minimum pulse pulse width 50ns of the INT signal trigger must be fulfilled Level detection INT H L Valid edge Interrupt request ER Clear by software 1 1 2 2 3 4 5 Internal clock CLKP divided by two Valid edge Interrupt requests ER Clear by software INT rising fallling Edge detection 1 1 2 2 3 4 5 Required to maintain the ...

Page 344: ...al inputs Inputs the signal to INT0 INT15 pins Operation mode Detection level bit LBn LAn n 0 15 Use as L level detection Sets to 00 Use as H level detection Sets to 01 Use as rise detection Sets to 10 Use as fall detection Sets to 11 Operation Data Direction bits Setting Port Function bit Setting To use INT0 pin input DDR24 0 Set to 0 PFR24 0 Set to 1 To use INT1 pin input DDR24 1 Set to 0 PFR24 ...

Page 345: ...s 0FFFBCh Interrupt level register ICR00 Address 00440h INT1 17 Address 0FFFB8h INT2 18 Address 0FFFB4h Interrupt level register ICR01 Address 00441h INT3 19 Address 0FFFB0h INT4 20 Address 0FFFACh Interrupt level register ICR02 Address 00442h INT5 21 Address 0FFFA8h INT6 22 Address 0FFFA4h Interrupt level register ICR03 Address 00443h INT7 23 Address 0FFFA0h INT8 24 Address 0FFF9Ch Interrupt leve...

Page 346: ...nterrupt enabling bits ENIR0 ENx x 0 7 and ENIR1 ENx x 8 15 to enable interrupts Use interrupt request bits EIRR0 ERx x 0 7 and EIRR1 ERx x 8 15 to clear interrupt requests Interrupt enabling bit En n 0 15 To disable interrupt requests Sets to 0 To enable interrupt requests Sets to 1 Interrupt request bit Ern n 0 15 To clear interrupt requests Writes 0 ...

Page 347: ... into standby stop mode make sure to disable unused external interrupts ENn 0 Note n 0 15 Minimum 3x CLKP peripheral clock is required for the pulse width to detect the edge presence when the request level is set to the edge request When waking up from STOP mode with edge detection enabled a minimum pulse width 50ns of the INT signal trigger must be fulfilled The interrupt request to the interrupt...

Page 348: ...332 Chapter 25 External Interrupt 8 Caution ...

Page 349: ...equest input pins DREQ0 DREQ1 DREQ2 DREQ3 for ch0 3 only External transfer request acceptance output pins DACK0 DACK1 DACK2 DACK3 for ch0 3 only DMA end output pins DEOP0 DEOP1 DEOP2 DEOP3 for ch0 3 only Fly by transfer memory to I O and I O to memory for ch0 3 only 2 cycle transfer Main Functions The following are the main functions related to data transfer by the DMA controller DMAC Data can be ...

Page 350: ... ERIR EDIR SADM SASZ 7 0 DADM DASZ 7 0 SADR DADR Read Write Access address Selector Selector Selector Counter X bus To interrupt controller IRQ 4 0 Priority circuit Peripheral activation request stop input Write back Write back Buffer Selector Counter Buffer MCLREQ Read write control To bus controller DMA transfer request to the bus controller DMA activation source selection circuit request accept...

Page 351: ...d start is disabled or temporarily stopped 24 31 23 16 15 08 07 00 ch 0 ch 0 ch 1 ch 1 ch 2 ch 2 ch 3 ch 3 ch 4 ch 4 ch 0 ch 0 ch 1 ch 1 ch 2 ch 2 ch 3 ch 3 ch 4 ch 4 bit Control status register A Control status register B DMACA0 Control status register A Control status register B DMACB0 DMACA1 Control status register A Control status register B Control status register A Control status register B ...

Page 352: ...MA transfer when a transfer request is generated and accepted All transfer requests that are generated for a deactivated channel are disabled When the transfer on an activated channel reaches the specified count this bit is set to 0 and transfer stops The transfer can be forced to stop by writing 0 to this bit Be sure to stop a transfer forcibly 0 write only after temporarily stopping DMA using th...

Page 353: ... 1 is written to this bit a transfer request is generated when write operation to the register is completed and transfer on the corresponding channel is started However if the corresponding channel is not activated operations on this bit are disabled If starting by a write operation to the DMAE bit and a transfer request occurring due to this bit are simultaneous the transfer request is enabled an...

Page 354: ...uest 00000 Activation by hardware prohibited not available 00001 01101 Setting prohibited Setting prohibited 01110 External DMA pin high level or rising edge 01111 External DMA pin low level or falling edge 10000 0000 0 External Interrupt 0 10001 0000 1 External Interrupt 1 10010 0000 2 External Interrupt 2 10011 0000 3 External Interrupt 3 10100 0000 4 Reload Timer 0 10101 0000 5 Reload Timer 1 1...

Page 355: ... select the source of a transfer request note that the software transfer request by the STRG bit function is always valid regardless of the setting of these bits As listed in Table 2 2 Settings for Extended Transfer Request Sources Table 2 2 Settings for Extended Transfer Request Sources IS EIS RN Function Transfer stop request 10000 0001 16 External Interrupt 0 10001 0001 17 External Interrupt 1 ...

Page 356: ... 2 RX available 10101 0011 53 USART LIN 2 TX 10110 0011 54 USART LIN 3 RX available 10111 0011 55 USART LIN 3 TX 11000 0011 56 USART LIN FIFO 4 RX available 11001 0011 57 USART LIN FIFO 4 TX 11010 0011 58 USART LIN FIFO 5 RX available 11011 0011 59 USART LIN FIFO 5 TX 11100 0011 60 USART LIN FIFO 6 RX available 11101 0011 61 USART LIN FIFO 6 TX 11110 0011 62 USART LIN FIFO 7 RX available 11111 001...

Page 357: ...100 0101 84 Input Capture 4 10101 0101 85 Input Capture 5 10110 0101 86 Input Capture 6 10111 0101 87 Input Capture 7 11000 0101 88 Output Compare 0 11001 0101 89 Output Compare 1 11010 0101 90 Output Compare 2 11011 0101 91 Output Compare 3 11100 0101 92 Output Compare 4 11101 0101 93 Output Compare 5 11110 0101 94 Output Compare 6 11111 0101 95 Output Compare 7 10000 0110 96 Programmable Pulse G...

Page 358: ...t register Transfer count register The DTC register stores the transfer count Each register has 16 bit length All registers have a dedicated reload register When the register is used for a channel that is enabled to reload the transfer count register the initial value is automatically written back to the register when the transfer is 10110 0110 102 Programmable Pulse Generator 6 10111 0110 103 Pro...

Page 359: ...s B DMACB0 to 4 Figure 2 3 Bit Configuration of Control Status Registers B DMACB0 to 4 Detailed Bit of Control Status Register B DMACB0 to 4 The following describeds the functions of the bits of control status register B DMACB0 to 4 Bits 31 to 30 TYPE TYPE Transfer type setting These bits are the transfer type setting bits and set the type of operation for the corresponding channel 2 cycle transfe...

Page 360: ...ers memory address When reset Initialized to 00B These bits are readable and writable Table 2 3 Settings for the Transfer Types TYPE Function 00B 2 cycle transfer initial value 01B Fly by Memory I O transfer 10B Fly by I O memory transfer 11B Setting disabled ...

Page 361: ...sed to select the transfer data width of the corresponding channel Transfer operations are repeated in units of the data width specified in this register for as many times as the specified count When reset Initialized to 00B These bits are readable and writable Table 2 4 Settings for Transfer Modes MOD Function 00B Block step transfer mode initial value 01B Burst transfer mode 10B Demand transfer ...

Page 362: ...d writable Bit 24 DADM Destination ADdr Count Mode select Transfer destination address count mode specification This bit specifies the address processing for the transfer destination address of the corresponding channel in each transfer operation An address increment is added or an address decrement is subtracted after each transfer operation according to the specified transfer destination address...

Page 363: ...oad Transfer source address register reload specification This bit controls reloading of the transfer source address register for the corresponding channel If this bit enables the reload operation the transfer source address register value is restored to its initial value after the transfer is completed If reloading of the counter is disabled a single shot operation occurs In single shot operation...

Page 364: ...ination after an error occurs The nature of the error that occurred is indicated by DSS2 to 0 Note that an interrupt occurs only for specific termination causes and not for all termination causes Refer to bits DSS2 to 0 which are Bits 18 to 16 When reset Initialized to 0 This bit is readable and writable Bit 19 EDIE EnD Interrupt Enable End interrupt output enable This bit controls the occurrence ...

Page 365: ...written value is 000 Bits 15 to 8 SASZ Source Addr count SiZe Transfer source address count size specification These bits specify the increment or decrement width for the transfer source address DMASA of the corresponding channel in each transfer operation The value set by these bits becomes the address increment decrement for each transfer unit The address increment decrement conforms to the inst...

Page 366: ...p of registers that store the transfer source transfer destination addresses Each register is 32 bits length Figure 2 4 Bit Configuration of the Transfer Source Transfer Destination Address Setting Registers DMASA0 to 4 DMADA0 to 4 shows the bit configuration of the transfer source transfer destination address setting registers DMASA0 to 4 DMADA0 to 4 Figure 2 4 Bit Configuration of the Transfer S...

Page 367: ...not possible for the DMAC s registers themselves 2 4 DMAC All Channel Control Register DMACR The DMAC all channel control register DMACR controls the operation of the all five DMAC channels Be sure to access this register using byte length This section describes the configuration and functions of the DMAC all channel control register DMACR Bit Configuration of DMAC All Channel Control Register DMA...

Page 368: ...If these bits are set DMA transfer is not performed on any channel before these bits are cleared When DMA transfer is activated after these bits are set all channels remain temporarily stopped Transfer requests that occur on channels for which DMA transfer is enabled DENB 1 while these bits are set are all enabled The transfer can be started by clearing all these bits When reset Initialized to 0 T...

Page 369: ...Controller DMAC Registers Pin Function of the DACK and DEOP and DREQ pins To use the DACK DEOP or DREQ pins for external transfer a switch must be made from the port function to the DMA pin function To make the switch set the PFR register ...

Page 370: ...nsfer until the next transfer request is received The block transfer unit is the specified block size BLK 3 0 of DMACA Burst transfer Transfer in response to one transfer request is carried out continuously for the number of times in the specified transfer count is reached The specified transfer count is the transfer count BLK 3 0 of DMACA X DTC 15 0 of DMACA X block size Demand transfer Transfer ...

Page 371: ...fer Specifying the address for a fly by transfer In a fly by transfer the value read from the transfer destination address register DMADA is used as the address for access The transfer source address register DMASA is ignored Be sure to specify an external area as the address to be set After receiving a transfer request DMA stores the address from the register in the temporary storage buffer and t...

Page 372: ...s block step or burst transfer select edge detection Falling edge detection Set with the transfer source selection register When IS 4 0 of DMACA 01110B Rising edge detection Set with the transfer source selection register When IS 4 0 of DMACA 01111B Level detection If the transfer type is demand transfer select level detection H level detection Set with the transfer source selection register When ...

Page 373: ...er all 32 bit areas can be specified using a transfer source transfer destination address A peripheral transfer request software transfer request or external pin DREQ edge input detection request can be selected as the transfer source The following are some features of a burst transfer When one transfer request is received transfer is performed continuously until the transfer count register reache...

Page 374: ...equest is checked While the external input level is within the range of the specified transfer request levels transfer is performed continuously without the request being cleared If the external input changes the request is cleared and the transfer stops at the transfer boundary This operation is repeated for the number of times specified by the transfer count Otherwise operations are the same as ...

Page 375: ...he block size a step transfer sequence is generated The following are some features of a step transfer If a transfer request is received the transfer request is cleared after one transfer operation and then the transfer is stopped The DMA transfer request to the bus controller is canceled Another request occurring during transfer is ignored Table 3 3 Specifiable transfer addresses demand transfer ...

Page 376: ...ad operation Block Size The unit and increment for transfer data is a set of the number set in the block size specification register x data width data Since the amount of data transferred in one transfer cycle is determined by the value specified as the data width one transfer unit is consists of the number of transfer cycles for the specified block size If a transfer request with a higher priorit...

Page 377: ...ce address register reloading above If only reloading of the transfer source transfer destination register is enabled restart after transfer is performed the specified number of times is not implemented and only the values of each address register are set Special examples of operating mode and the reload operation If transfer is performed in continuous transfer mode by external pin input level det...

Page 378: ...opped Refer to the description for the items related to the end code Do not set any of the DMAC s registers as the address register For demand transfer be sure to set an address in an external area for the transfer source transfer destination or both Do not let the DMAC transfer data to any of the DMAC s registers 3 5 Data Types Select the data length data width transferred in one transfer operati...

Page 379: ... or an interrupt request with a higher level than the hold suppress level set by the interrupt controller occurs DMAC temporarily cancels the transfer request via the bus controller at a transfer unit boundary one block to temporarily stop the transfer until the interrupt request is cleared In the meantime the transfer request is retained internally After the interrupt request is cleared DMAC reis...

Page 380: ...ccessed by DMA transfer DMA transfer is temporarily stopped When the external hold is released DMA transfer is restarted 3 9 Operation from Starting to End Stopping Starting of DMA transfer is controlled independently for each channel but before transfer starts the operation of all channels needs to be enabled This section describes operation from starting to end stopping Operation Start Enabling ...

Page 381: ...ated after transfer is performed the specified number of times Demand transfer Since only start requests from external pins are supported in demand transfer no clear signal is generated Temporary Stopping DMA transfer is stopped temporary in the following cases Setting of temporary stopping by writing to the control register Set independently for each channel or all channels simultaneously If temp...

Page 382: ...ions system peripheral The DMAC when it receives such a transfer stop request displays Transfer stop request as the end code and stops the transfer on the corresponding channel Table 3 6 Stopping due to an Error 1 A transfer stop request is issued when an error is detected For details of the conditions under which a transfer stop request is generated see the specifications for each peripheral circ...

Page 383: ...CS Be sure to clear the end code by writing 000B before restarting If reloading is enabled the transfer is automatically restarted At this point however the end code is not cleared and is retained until a new end code is written when the next transfer ends Since only one end source can be displayed in an end code the result after considering the order of priority is displayed when multiple sources...

Page 384: ...transfer for the transfer unit number set in the block size specification register x data width ends When higher priority transfer is completed transfer is restarted on the previous channel Figure 3 5 Timing Example in Fixed Mode Rotation mode ch 0 to ch 1 only When operation is enabled the initial states have the same order that they would have in fixed mode but at the end of each transfer operat...

Page 385: ...nput when a Demand Transfer Request is Stopped For 2 cycle transfer For a demand transfer be sure to set an address in an external area for the transfer source the transfer destination or both If the transfer type is external external Negate before the last sense timing of the clock in the L section of the external WRn pin output when accessing the transfer source for the last DMA transfer section...

Page 386: ...er After the external WRn pin output for the last DMA transfer goes to the H level negate DREQ while IORD is at the L level section where DACK L RD L If DREQ is negated later than this the negation may continue until the next transfer Figure 3 8 Negate timing example of the DREQ pin input for fly by write transfer Timing of the DREQ Pin Input for Continuing Transfer over the Same Channel For burst...

Page 387: ...ransfer destination is internal access DEOP is not output To use DEOP output it is necessary to enable the DEOP output using the port register If an External Pin Transfer Request is Reentered During Transfer For burst step and block transfers While the DACK signal is asserted within the DMAC the next transfer request if it is entered is disabled However since operation of the external bus control ...

Page 388: ...ller DMAC Operation AC Characteristics of DMAC DREQ pin input DACK pin output and DEOP pin output are provided as the external pins related to the DMAC Output timing is synchronized with external bus access refer to the AC standard for the DMAC ...

Page 389: ... wait Interrupt clear DMA transfer end DMA interrupted BLK 0 DTC 0 DMA stop DENB 1 DENB 0 Write back the address transfer count and number of blocks Number of blocks 1 Activation request One time access for fly by Reload enable Only when the peripheral interrupt activation source is selected Calculate the address for transfer source address access Calculate the address for transfer destination add...

Page 390: ...back the address transfer count and number of blocks Number of blocks 1 Interrupt clear One time access for fly by Reload enable Only when the peripheral interrupt activation source is selected Calculate the address for transfer source address access Calculate the address for transfer destination address access Transfer count 1 Interrupt cleared Burst transfer Can be activated by all activation so...

Page 391: ...ral interrupt activation source is selected Calculate the address for transfer source address access Calculate the address for transfer destination address access Number of transfer 1 Interrupt cleared None Demand transfer Only requests level detection from the external pin DREQ are accepted Activation by other sources is disabled Access to an external area is required since access to an external ...

Page 392: ... bus F bus D bus X bus I bus F bus RAM CPU MB91460 Read cycle Read cycle Read cycle IO Bus controller DMAC RAM CPU MB91460 Data buffer Bus controller Data buffer Write cycle Write cycle Write cycle IO DMAC RAM CPU MB91460 IO DMAC RAM CPU MB91460 IO DMAC RAM CPU MB91460 IO DMAC RAM CPU MB91460 IO External area external area transfer External area internal RAM area transfer External area built in I ...

Page 393: ...ler DMAC RAM CPU MB91460 IO Bus controller DMAC RAM CPU MB91460 IO D bus X bus I bus F bus D bus X bus I bus F bus Bus controller DMAC RAM CPU MB91460 IO Bus controller DMAC RAM CPU MB91460 IO Read cycle Read cycle Read cycle Write cycle Write cycle Write cycle Built in I O area internal RAM area transfer Internal RAM area external area transfer Internal RAM area built in I O area transfer Externa...

Page 394: ... RD or DACK memory Memory write by WR or CSn I O read by WR or DACK D bus X bus I bus F bus Bus controller DMAC RAM CPU MB91460 I O I O I O D bus X bus I bus F bus Bus controller DMAC RAM CPU MB91460 I O Read cycle Read cycle Fly by transfer memory to I O Fly by transfer I O to memory External bus I F Data buffer Data buffer ...

Page 395: ...erface 6 1 Input Timing of the DREQx Pin The DREQx pin is a DMA start request signal If the pin is also used as a port enable the DREQ input using the PFR register This section shows the input timing of the DREQx pin Timing of Transfer Other Than Demand Transfer For transfer other than demand transfer set the DMA start source to edge detection Although there is no rule for rise fall timing use thr...

Page 396: ... makes the DACK timing identical to the timing of DMA used in FR30 series devices This section provides the timing charts for the DACK pin in FR30 compat ible mode for the following examples of transfer mode setting 2 cycle transfer mode Fly by transfer mode Transfer Mode Settings Set the transfer mode using the PFR register corresponding to the DACK pin When setting PFR match the transfer mode 2 ...

Page 397: ...AKxx 101B AKxx is the setting value in the PFR register that corresponds to the DMA channel DACK AKxx 010B DACK AKxx 011B DACK AKxx 110B RD DQMU L WR WRn IORD IOWR DACK AKxx 111B Same timing as the chip select DACK AKxx 001B DACK AKxx 010B Fly by transfer setting disabled DACK AKxx 011B Fly by transfer setting disabled DACK AKxx 100B Fly by transfer setting disabled Memory to I O I O to memory Mem...

Page 398: ...382 Chapter 26 DMA Controller 6 DMA External Interface ...

Page 399: ...ity 1 Other The software generates releases interrupt request Real time OS uses the delayed interrupt for task switching 3 Configuration Figure 3 1 Configuration Diagram Figure 3 2 List of Registers Delay interrupt control circuit Software request Interrupt request 63 Delay interrupt Delay interrupt control circuit Interrupt request 63 Delay interrupt control bit DLYI DICR bit 0 0 1 Without interr...

Page 400: ... OS returns the interrupt with the highest priority sequence takes place because an interrupt service is prohibited in OS 5 When the interrupt with the highest priority is completed delayed interrupt takes place 6 In delayed interrupt delayed interrupt is released 7 Returned from the delayed interrupt dispatched to task B 7 6 5 4 3 2 1 0 bit DLYI 0 Initial value RX WX RX WX RX WX RX WX RX WX RX WX...

Page 401: ...interrupt request bit DICR DLYI performs this function The delayed interrupt does not have an interrupt request enable bit 8 Caution The delay interrupt request bit is the same as general interrupt request flags It should be used to clear delayed interrupt request bit in an interrupt routine in addition to switching tasks The delayed interrupt function can use real time OS REALOS As a result the d...

Page 402: ...386 Chapter 27 Delayed Interrupt 8 Caution ...

Page 403: ...om MSB to LSB 0 detection Detects the first 0 changing position 1 detection Detects the first 1 changing position Changing position detectionDetects the position where data first changes Quantity 1 Other Can read internal data This can be used to restore the previous state when it is used for bit search during interrupt service or handler 0 position register Detection circuit 0 position 1 pos and ...

Page 404: ...Changing position detection data register Bit search Detection circuit 0 1 Changing positions BSRR Detection result Lowest four bits of the address Operation selection for BSD0 BSD1 BSDC 0000 0100 1000 0 detection 1 detection Changing position detection Detection mode selection Address decoder Run only Write only Detection data BSD1 Bit search ...

Page 405: ...data written in the order of MSB bit31 to LSB bit0 During change position detection the position where a value different from MSB bit31 is first detected is stored for data written in the order of bit30 to LSB bit0 The register BSD0 used for 0 detection and the BSRC register used for changing position detection are write only The value during read operation is indefinite Data saved in the bit sear...

Page 406: ...nging position detection register BSDC can be read Data last written can be read However the type of result cannot be identified Information on 0 detection 1 detection or changing position detection is not included A 0 can be read at detection position bit31 MSB and continues reading 31 at detection position bit0 LSB by adding 1 at the next position toward bit0 LSB A value of 32 is read when not d...

Page 407: ...tion starts once data is written 3 Detect 1 scan starting with the MSB 4 Detected bit position 5 Detection result If 1 does not exist That is if numeric value is 00000000H value of 32 is returned as detection result Execution example Write data Read value Decimal notation 00100000000000000000000000000000B 20000000H Æ 2 00000001001000110100010101100111B 01234567H Æ 7 0000000000000011111111111111111...

Page 408: ...B 00000001H Æ 31 00000000000000000000000000000000B 00000000H Æ 32 11111111111111111111000000000000B FFFFF000H Æ 20 11111000010010011110000010101010B F849E0AAH Æ 5 10000000000000101010101010101010B 8002AAAAH Æ 1 11111111111111111111111111111111B FFFFFFFFH Æ 32 Table 5 1 The Relationship Between the Bit Position and the Value to be Returned Decimal Notation Detected bit position Return value Detecte...

Page 409: ...ion detection data register BSD0 Refer to 7 1 Converted value read Detection result register BSRR Refer to 7 2 Table 6 2 Setting Required for Using One Position Detection Setting Setting register Setting method Data write scan start One position detection data register BSD1 Refer to 7 1 Converted value read Detection result register BSRR Refer to 7 2 Table 6 3 Setting Required for Using Changing P...

Page 410: ...er 1 Reads data from the one detection data register and saves the contents evacuation 2 The Bit search is used 3 Writes data evacuated in Item 1 in the one detection data register restoration Using the above procedures the value to be read next from the detection result register is the one that was written in the bit search executed in 1 or before The bit search state can be correctly restored us...

Page 411: ...sition detection The data registers 0 detection 1 detection changing position detection is a write only and accessed by word However the 1 detection read address is assigned to an internal data register for restoration so that you can restore previous bit search state Refer to 7 3 How is a result read Page No 394 The 0 detection register BS0 1 detection register BSD1 and changing position detectio...

Page 412: ...396 Chapter 28 Bit Search 8 Caution ...

Page 413: ...ize and access type 2 Operand Address Breakpoints and 2 Instruction Address Breakpoints 2 Operand Address Breakpoints and 2 Data Value Breakpoints 2 Masks possible to assign reduces the number of breakpoints 2 Range Functions Break Trigger programmable on resource interrupts MPU functionality User and SuperVisor permission for read write execute Default permissions for the whole MCU address range ...

Page 414: ...as mask registers then Also mask able is a break address range made with two points and one mask register Two absolute address ranges for operand breakpoints can be defined where 2 or 4 out of 4 operand breakpoint registers are assigned for the range Operand breaks can be selected for datasizes byte halfword and word on access types read read modify write and write 2 Operand Data Value Breakpoints...

Page 415: ...AD0 register The same applies for EP0 and ER0 which enables the use of the oppo site BAD2 register for the mask information Example CTC 00 Type Instruction Address Break EP1 1 Enable break point address BAD1 EM0 1 Set mask BAD0 for break address BAD1 BAD1 0x12345678 Set break address BAD0 0x00000FFF Set break mask Break occurs at 0x12345000 to 0x12345FFF On break at BAD 3 0 the respective flags BD...

Page 416: ... break address BAD1 BAD1 0x12345678 Set break address BAD0 0x00000FFF Set break mask Break occurs at 0x12345000 to 0x12345FFF On break at BAD 3 0 the respective flags BD 3 0 in the break interrupt request register BIRQ will be set to 1 They have to be reset by software in the operand break exception routine Channels 0 and 1 BAD0 BAD1 can be set up to function as address range match Setting the ER0...

Page 417: ...es can also be specified by the control register BCR0 bits OBS 1 0 and OBT 1 0 When the mask function is disabled by setting EM1 EM0 0 all bits effective the rela tionship between breakpoint setting and break by access address is shown below Table 3 2 Operand Break Detection Status Bits BD BD1 BD0 0 1 Match on point operand address 0x12345200 or Match on point operand address 0x22345200 etc 1 0 Ma...

Page 418: ...alue stored in BAD1 and 1 mask register BAD2 is avail able for masking the operand address BAD3 which is being accessed Mask registers BAD2 and BAD0 can be enabled with EM1 and EM0 The data on which a break should be executed must be masked by a data mask on the bus requiring 32 bit setting considering the address and data length see table below This is required due to the byte position of the ope...

Page 419: ...ata value break together is enabled with setting both EP3 and EP1 and or both EP2 and EP0 together with setting the bit COMB 1 for the data value break mode set with CTC 11 In other words a break in channel 0 will occur at a match on operand address in BAD2 and a match on data value in BAD0 A break in channel 1 will occur at a match on operand address in BAD3 and a match on data value in BAD1 It i...

Page 420: ...of the operand break size and type definitions OBS OBT including read modify write With the introduction of the SuperVisor mode a defini tion of User and SuperVisor permissions is possible Table 3 5 Operand address and data value break combinations EP3 2 EP1 0 COMB Function 0 0 0 No break detection 0 1 0 Independent data break match value on any operand address 1 0 0 Independent Operand break matc...

Page 421: ...fig register space of the EDSU is protected against random access in User mode Only in SuperVisor mode or Emulation mode the register file enables write access For configuration a system interrupt INT 5 was defined which switches in SuperVisor mode SV bit remains set during the execution of the INT 5 ISR Except debugger interrupts by the emulator and NMI the SuperVisor ISR is not interruptible Exc...

Page 422: ...ctor Decimal Hexa decimal Setting Register Register address Offset Default Vector address CPU supervisor mode INT 5 instruction 5 05 0x3E8 0x000FFFE8 Memory protection exception 6 06 0x3E4 0x000FFFE4 INTE instruction 9 09 0x3D8 0x000FFFD8 Instruction break exception 10 0A 0x3D4 0x000FFFD4 Operand break exception 11 0B 0x3D0 0x000FFFD0 Step trace trap 12 0C 0x3CC 0x000FFFCC NMI interrupt tool 13 0D...

Page 423: ...H BOAC R 00000000 00000000 00000000 00000000 F010H BIRQ R W 00000000 00000000 00000000 00000000 F014H F01FH reserved F020H BCR0 R W 00000000 00000000 00000000 F024H BCR1 R W 00000000 00000000 00000000 F028H BCR2 R W 00000000 00000000 00000000 F02CH BCR3 R W 00000000 00000000 00000000 F030H BCR4 R W 00000000 00000000 00000000 F034H BCR5 R W 00000000 00000000 00000000 F038H BCR6 R W 00000000 0000000...

Page 424: ...XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F09CH BAD7 R W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0A0H BAD8 R W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0A4H BAD9 R W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0A8H BAD10 R W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0ACH BAD11 R W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0B0H BAD12 R W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0B4H BAD13 R W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0B...

Page 425: ...W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0DCH BAD23 R W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0E0H BAD24 R W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0E4H BAD25 R W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0E8H BAD26 R W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0ECH BAD27 R W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0F0H BAD28 R W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0F4H BAD29 R W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXX...

Page 426: ...er visor default Read permission register BIT 14 SW Super visor default Write permission register BIT 13 SX Super visor default eXecute permission register BIT 12 UR User default Read permission register 0 Super visor is not permitted to read data 1 Super visor is permitted to read data default 0 Super visor is not permitted to write data 1 Super visor is permitted to write data default 0 Super vi...

Page 427: ...sses can cause break function Important Note for FDMA Only DMA accesses over D Bus were detected The operands for an explicite DMA trig ger condition have to be located in the D Bus address area This is the case for D bus RAM CAN and all R Bus resources in the MB91460 family Otherwise the DMA transfer could not be recognized by the EDSU This function was mainly intendet to disable the trigger on D...

Page 428: ... not executed commands Commands after delayed slot instruction Consecutive break conditions which are pre fetched are not allowed to set flags Only the instruction at which the break condition occures at first time can set status bits accordingly Nested Instruction breaks are not allowed break within the break handler ISR BIT 5 4 SINT 1 0 Select resource INTerrupt source SINT1 and SINT0 select the...

Page 429: ...et to 1 then a Tool NMI will be generated on a transmit interrupt event at source channels 0 to 3 set by TXINT 1 0 Setting EINTT to 0 disables this function Remark If SINT 1 0 is set to 11 this bit enables the interrupt of CAN channel 1 CAN has one interrupt request for both reception and transmission BIT 0 EINTR Enable INTerrupt on Receive If EINTR is set to 1 then a Tool NMI will be generated on...

Page 430: ... indication register can be read only Access Type Capture Register In case of a trap caused by a memory protection violation or an operand data value break condition the status bits 12 8 capture type information about the break causing operand access In case of a memory protection fault due to the violation of execution permissions this information is also captured regardless if there was an activ...

Page 431: ...te access to this bit will be ignored RST is cleared after BSTAT is read read from any byte address within the 32 bit word RST has same behaviour for read and read modify write access The RST bit can be used for reset detection It is set in any case of operation initialization reset is triggered Debug monitor software can use this to detect if the communication device to the debugger front end nee...

Page 432: ...vel on the signal line This bit is read only It can be set to 0 by clearing the appropriate interrupt bit in the selected resource Remark If SINT 1 0 is set to 11 this bit indicates the interrupt of CAN channel 1 CAN has one interrupt request for both reception and transmission BIT 0 INTR INTerrupt on Receive source INTR reflects the status of the receive interrupt source channels 0 to 3 can be se...

Page 433: ...ch could build a range comparator by setting the range enable bit Such a range comparator pair is connected to the instruction address operand address or the data value information selected by the comparator type configuration For detection of combined operand address and data value breaks two of such comparator pairs are combined to gether Than the break detection BD bits are set only if both con...

Page 434: ...led address range function also valid for the other pairs of BD bits in neighbourhood If the operand address range function is enabled with ER0 in addition to the point enables EP1 and EP0 then the BD1 and BD0 detection bits are set in the following manner Table 4 2 BD Coding for Match on Start Endoint or Range BD1 BD0 Compare value Instruction Operand Address Data Value 0 0 No match Default 0 1 M...

Page 435: ...5 Point1 EP1 OA1 BD5 BAD6 Point2 Mask1 EP2 EM1 range 1 ER1 DT0 BD6 BAD7 Point3 EP3 DT1 BD7 BCR2 BAD8 Point0 Mask0 EP0 EM0 range 0 ER0 OA0 BD8 BAD9 Point1 EP1 OA1 BD9 BAD10 Point2 Mask1 EP2 EM1 range 1 ER1 DT0 BD10 BAD11 Point3 EP3 DT1 BD11 Bit no Read write Default value X X X X X X X X EDSU Ch Config Register 0 byte 0 Address F020H 31 30 29 28 27 26 25 24 SRX1 SW1 SRX0 SW0 URX1 UW1 URX0 UW0 Bit n...

Page 436: ... 0 both IA ranges define execute permissions CTC 1 both OA ranges define read write permissions and BCR3 BAD12 Point0 Mask0 EP0 EM0 range 0 ER0 OA0 BD12 BAD13 Point1 EP1 OA1 BD13 BAD14 Point2 Mask1 EP2 EM1 range 1 ER1 DT0 BD14 BAD15 Point3 EP3 DT1 BD15 BCR4 BAD16 Point0 Mask0 EP0 EM0 range 0 ER0 OA0 BD16 BAD17 Point1 EP1 OA1 BD17 BAD18 Point2 Mask1 EP2 EM1 range 1 ER1 DT0 BD18 BAD19 Point3 EP3 DT1...

Page 437: ...ster for range 0 Setting valid for CTC 0 or CTC 2 Instruction address range comparator Setting valid for CTC 1 Operand address range comparator BIT 20 SW1 Super visor Write permission register for range 0 Setting valid for CTC 1 Operand address range comparator 0 Super visor has no execute permission on address range 1 default 1 Super visor has execute permission on address range 1 0 Super visor h...

Page 438: ...ddress range comparator Group of Channels Mode Configuration Register BIT 15 MPE Memory Protection Enable 0 User has no execute permission on address range 1 default 1 User has execute permission on address range 1 0 User has no read permission on address range 1 default 1 User has read permission on address range 1 0 User has no write permission on address range 1 default 1 User has write permiss...

Page 439: ... 0 define a data value range DT1 DT0 by setting ER0 1 the break detection bits of each channel are AND combined with the ORed channels of the opposite range comparator break detection outputs BIRQ_BD3 BD3 BD1 BD0 BIRQ_BD2 BD2 BD1 BD0 BIRQ_BD1 BD1 BD3 BD2 BIRQ_BD0 BD0 BD3 BD2 This offers the same interpretation of the BIRQ break detction bits see table 4 2 for coding of match on start point range o...

Page 440: ... break detection channels 3 and 2 The compare value for CMP1 can be assigned either to the instruction address IA or to the operand address OA CMP0 com bines the break detection channels 1 and 0 The compare value for CMP0 can be assigned to the instruction ad dress IA to the operand address OA or to the data value DT The table above defines the input compare values for CMP1 and CMP0 depending on t...

Page 441: ... be compared with the point 2 register content BAD index 2 group offset BAD2 for group 0 channel 2 BAD6 for group 1 channel 2 The input value and the point value is masked if the mask function is enabled by EM1 On a compare match a break exception will be executed CTC and MPE control the selection of the input value and the type of the break excep tion EP2 controls in addition to enabling and allo...

Page 442: ...enable EP0 and EP1 which normally are set in this case Thus point 0 could be used for storing the mask value for both comparators CMP1 and CMP0 and the exception described in the paragraph above did not apply for this case Enable Mask And Range Register BIT 3 EM1 Enable Mask for CMP1 If EM1 is enabled the comparator CMP1 matches only these bit positions which are set to 0 and are not masked by the...

Page 443: ...nel BAD x 3 and BAD x 2 and the mask is stored in Point 0 BAD x 0 Otherwise Point 1 and Point 0 are taken from BAD x 1 and BAD x 0 the mask is stored in Point 2 BAD x 2 The x is the group offset and calculates by the group index multiplied with 4 Break Address Data register BAD0 BAD31 The BADx registers define 32 break point addresses data values or mask information for the 8 groups of channels Fo...

Page 444: ...ue for break point 2 of CMP1 In range mode set with ER1 the register value of BAD2 functions as lower address limit In addition BAD2 could be used as mask register This register sets the 32 bit comparison value for break point 3 of CMP1 In range mode set with ER1 the register value of BAD3 functions as upper address limit BAD1 BAD5 BAD9 BAD29 R W Address 0 1 2 3 F084H XXXXXXXX XXXXXXXX XXXXXXXX XX...

Page 445: ...S1 OBS0 OBT1 OBT0 EP3 EP2 EP1 EP0 EM1 EM0 ER1 ER0 BAD31 0xF0FC SR SW SX UR UW UW FCPU FDMA EEMM PFD SINT1 SINT0 EINT1 EINT0 EINTT EINTR BAD2 0xF088 BSTAT 0xF004 ro ro ro ro ro ro ro ro ro ro 0xF010 BIRQ BD23 BD22 BD21 BD20 BD19 BD18 BD17 BD16 BD15 BD14 BD13 BD12 BD11 BD10 BD9 BD8 BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 BCR7 0xF03C BCR0 0xF020 ro ro Device select 31 24 23 16 15 8 7 0 BCTRL 0xF000 Rst Break...

Page 446: ...oint 1 Point 0 Mask 0 Value BCR0 BAD3 BAD2 BAD1 BAD0 CTC CTC OBS Match IA OA CMP1 BD3 BD2 CMP0 IA OA DT BD1 BD0 IA OA IA OA DT Comparator GROUP 1 Point 3 Point 2 Mask 1 Value Point 1 Point 0 Mask 0 Value BAD7 BAD6 BAD5 BAD4 BCR1 BD0 BD1 BD2 BD3 OBS0 BD4 BD5 BD6 BD7 OBS1 BCR1 BCR0 Break Detection Evaluation Figure 5 2 Comparator Group Structure drawn for two groups ...

Page 447: ...CLK TC10_0 Clock Monitor Output Port 00 P00_7 P00_7 TP04_0 General purpose I O This function is enabled in the single chip mode or by setting the corresponding PFR to 0 D31 I O pin for bit 31 of the external data bus This function is enabled when the external bus is enabled P00_6 P00_6 TP04_0 General purpose I O This function is enabled in the single chip mode or by setting the corresponding PFR t...

Page 448: ...6 TP04_0 General purpose I O This function is enabled in the single chip mode or by setting the corresponding PFR to 0 D22 I O pin for bit 22 of the external data bus This function is enabled when the external bus is enabled P01_5 P01_5 TP04_0 General purpose I O This function is enabled in the single chip mode or by setting the corresponding PFR to 0 D21 I O pin for bit 21 of the external data bu...

Page 449: ...3 TP04_0 General purpose I O This function is enabled in the single chip mode or by setting the corresponding PFR to 0 D11 I O pin for bit 11 of the external data bus This function is enabled when the external bus is enabled P02_2 P02_2 TP04_0 General purpose I O This function is enabled in the single chip mode or by setting the corresponding PFR to 0 D10 I O pin for bit 10 of the external data bu...

Page 450: ...rpose I O This function is enabled in the single chip mode or by setting the corresponding PFR to 0 D0 I O pin for bit 0 of the external data bus This function is enabled when the external bus is enabled Port 04 P04_7 P04_7 TP04_0 General purpose I O This function is enabled in the single chip mode or by setting the corresponding PFR to 0 A31 I O pin for bit 31 of the external address bus This fun...

Page 451: ...4_0 General purpose I O This function is enabled in the single chip mode or by setting the corresponding PFR to 0 A21 I O pin for bit 21 of the external address bus This function is enabled when the external bus is enabled P05_4 P05_4 TP04_0 General purpose I O This function is enabled in the single chip mode or by setting the corresponding PFR to 0 A20 I O pin for bit 20 of the external address b...

Page 452: ...04_0 General purpose I O This function is enabled in the single chip mode or by setting the corresponding PFR to 0 A10 I O pin for bit 10 of the external address bus This function is enabled when the external bus is enabled P06_1 P06_1 TP04_0 General purpose I O This function is enabled in the single chip mode or by setting the corresponding PFR to 0 A9 I O pin for bit 9 of the external address bu...

Page 453: ...led in the single chip mode or by setting the corresponding PFR to 0 RDY Input pin for external wait if RDY enabled for the corresponding CS area This function is enabled when the external bus is enabled P08_6 P08_6 TP04_0 General purpose I O This function is enabled in the single chip mode or by setting the corresponding PFR to 0 BRQ Input pin for external bus request if sharing enabled for the c...

Page 454: ...when the external bus is enabled P09_4 P09_4 TP04_0 General purpose I O This function is enabled in the single chip mode or by setting the corresponding PFR to 0 CSX4 Output pin for external bus chip select area 4 This function is enabled when the external bus is enabled P09_3 P09_3 TP04_0 General purpose I O This function is enabled in the single chip mode or by setting the corresponding PFR to 0...

Page 455: ...sponding PFR to 0 WEX Output pin for external bus write strobe This function is enabled when the external bus is enabled P10_2 P10_2 TP04_0 General purpose I O This function is enabled in the single chip mode or by setting the corresponding PFR to 0 BAAX Output pin for external bus burst access This function is enabled when the external bus is enabled P10_1 P10_1 TP04_0 General purpose I O This fu...

Page 456: ...ose I O DACKX2 Output pin for DMA transfer request acknowledgement P12_0 P12_0 TP04_0 General purpose I O DREQ2 Input pin for DMA transfer request Port 13 P13_7 P13_7 TP04_0 General purpose I O DEOP1 Output pin for DMA end of transfer P13_6 P13_6 TP04_0 General purpose I O DEOTX1 Input pin for DMA transfer stop request DEOP1 Output pin for DMA end of transfer P13_5 P13_5 TP04_0 General purpose I O...

Page 457: ...pose I O ICU3 Data sample input pin for input capture ICU 3 TIN3 Event input pin for the reload timer RLT 3 TTG11 3 Event input pin for the programmable pulse generators PPG 11 and PPG 3 P14_2 P14_2 TP00_0 General purpose I O ICU2 Data sample input pin for input capture ICU 2 TIN2 Event input pin for the reload timer RLT 2 TTG10 2 Event input pin for the programmable pulse generators PPG 10 and PP...

Page 458: ..._0 General purpose I O PPG15 Waveform output pin for programmable pulse generator PPG 15 ATGX A D converter external trigger input P16_6 P15_6 TP00_0 General purpose I O PPG14 Waveform output pin for programmable pulse generator PPG 14 PFM Waveform output pin for pulse frequency modulator PFM P16_5 P15_5 TP00_0 General purpose I O PPG13 Waveform output pin for programmable pulse generator PPG 13 S...

Page 459: ...0 Port 18 P18_7 P18_7 TP00_0 General purpose I O P18_6 P18_6 TP00_0 General purpose I O SCK7 Clock I O pin for LIN USART 7 ZIN3 8 bit reset input pin of the Up Down Counter UDC 2 3 CK7 Input for the 16 bit I O Timer FRT 7 P18_5 P18_5 TP00_0 General purpose I O SOT7 Serial data output pin for LIN USART 7 BIN3 8 bit down count input pin of the Up Down Counter UDC 2 3 P18_4 P18_4 TP00_0 General purpo...

Page 460: ...CK3 Clock I O pin for LIN USART 3 ZIN1 8 bit reset input pin of the Up Down Counter UDC 0 1 CK3 Input for the 16 bit I O Timer FRT 3 P20_5 P20_5 TP00_0 General purpose I O SOT3 Serial data output pin for LIN USART 3 BIN1 8 bit down count input pin of the Up Down Counter UDC 0 1 P20_4 P20_4 TP00_0 General purpose I O SIN3 Serial data input pin for LIN USART 3 AIN1 8 bit up count input pin of the Up...

Page 461: ...LIN USART 0 Port 22 P22_7 P22_7 TP02_0 General purpose I O SCL1 Serial clock I O pin for I2C 1 P22_6 P22_6 TP02_0 General purpose I O SDA1 Serial data I O pin for I2C 1 INT15 External interrupt request input pin for INT 15 P22_5 P22_5 TP02_0 General purpose I O SCL0 Serial clock I O pin for I2C 0 P22_4 P22_4 TP02_0 General purpose I O SDA0 Serial data I O pin for I2C 0 INT14 External interrupt req...

Page 462: ...nput pin for CAN 0 INT8 External interrupt request input pin for INT 8 Port 24 P24_7 P24_7 TP02_0 General purpose I O INT7 External interrupt request input pin for INT 7 SCL3 Serial clock I O pin for I2C 3 P24_6 P24_6 TP02_0 General purpose I O INT6 External interrupt request input pin for INT 6 SDA3 Serial data I O pin for I2C 3 P24_5 P24_5 TP02_0 General purpose I O INT5 External interrupt reque...

Page 463: ..._0 General purpose I O SMC2M3 PWM output 2M stepper motor controller 3 AN31 Analog input pin 31 for the A D converter 1 P26_6 P26_6 TP05_0 General purpose I O SMC2P3 PWM output 2P stepper motor controller 3 AN30 Analog input pin 30 for the A D converter 1 P26_5 P26_5 TP05_0 General purpose I O SMC1M3 PWM output 1M stepper motor controller 3 AN29 Analog input pin 29 for the A D converter 1 P26_4 P2...

Page 464: ...tput 2M stepper motor controller 0 AN19 Analog input pin 19 for the A D converter 1 P27_2 P27_2 TP05_0 General purpose I O SMC2P0 PWM output 2P stepper motor controller 0 AN18 Analog input pin 18 for the A D converter 1 P27_1 P27_1 TP05_0 General purpose I O SMC1M0 PWM output 1M stepper motor controller 0 AN17 Analog input pin 17 for the A D converter 1 P27_0 P27_0 TP05_0 General purpose I O SMC1P...

Page 465: ... 3 for the A D converter 1 P29_2 P29_2 TP03_0 General purpose I O AN2 Analog input pin 2 for the A D converter 1 P29_1 P29_1 TP03_0 General purpose I O AN1 Analog input pin 1 for the A D converter 1 P29_0 P29_0 TP03_0 General purpose I O AN0 Analog input pin 0 for the A D converter 1 Port 30 P30_7 P30_7 TP08_0 General purpose I O V3 Analog input pin external reference voltage V3 LCD controller P30...

Page 466: ..._0 P31_0 TP06_0 General purpose I O SEG32 Segment driver output pin 32 LCD controller Port 32 P32_7 P32_7 TP06_0 General purpose I O SEG31 Segment driver output pin 31 LCD controller P32_6 P32_6 TP06_0 General purpose I O SEG30 Segment driver output pin 30 LCD controller SCK15 Clock I O pin for LIN USART 15 P32_5 P32_5 TP06_0 General purpose I O SEG29 Segment driver output pin 29 LCD controller SO...

Page 467: ...purpose I O SEG18 Segment driver output pin 18 LCD controller SCK12 Clock I O pin for LIN USART 12 P33_1 P33_1 TP06_0 General purpose I O SEG17 Segment driver output pin 17 LCD controller SOT12 Serial data output pin for LIN USART 12 P33_0 P33_0 TP06_0 General purpose I O SEG16 Segment driver output pin 16 LCD controller SIN12 Serial data input pin for LIN USART 12 Port 34 P34_7 P34_7 TP06_0 Gener...

Page 468: ...roller SCK9 Clock I O pin for LIN USART 9 P35_5 P35_5 TP06_0 General purpose I O SEG5 Segment driver output pin 5 LCD controller SOT9 Serial data output pin for LIN USART 9 P35_4 P35_4 TP06_0 General purpose I O SEG4 Segment driver output pin 4 LCD controller SIN9 Serial data input pin for LIN USART 9 P35_3 P35_3 TP06_0 General purpose I O SEG3 Segment driver output pin 3 LCD controller P35_2 P35_...

Page 469: ...p TP00_0 Up Down switch CH AH switch Stop 4 mA TP01_0 CH AH switch Stop In Out 4 mA ADC DAC TP02_0 CH AH switch Stop 3 mA I2C TP03_0 Up Down switch CH AH switch Stop Input 4 mA AN TP04_0 Up Down switch CH AH TTL Switch Stop 4 mA External Bus TP05_0 CH AH switch Stop Input 30 mA SMC ADC TP06_0 CH AH switch Stop 4 mA LCD COM SEG TP07_0 CH AH switch Stop In Out 4 mA LCD V0 V1 V2 TP08_0 CH AH switch S...

Page 470: ...tion on page 498 7 Certain ports have programmable Pull Ups Pull Downs 50 kOhm which are enabled bit wise by their Pull Up Pull Down Enable Registers PPER and Pull Up Pull Down Control Registers PPCR See section Programmable Pull Up Pull Down Resistors on page 500 8 Each port has one or two Port Function Registers PFR and if necessary Extra PFR EPFR Together they can serve up to 3 resource I O s p...

Page 471: ...on page 458 LIN USART outputs SOT must be enabled additionally by setting the SOE bit in the LIN USART control 15 Resource bidirectional signals e g SCK of the LIN USART are enabled by setting the corresponding PFR and or EPFR bit in the port The signal direction is controlled by the setup of the resource e g via the output enable bits Details see section Port Function Register Setup on page 458 ...

Page 472: ...al PODR Port Output Drive Register Address PDR 0xE00h optional PILR Port Input Level selection Register Address PDR 0xE40h optional EPILR Port Input Level selection Register Address PDR 0xE80h optional PPER Port Pull up down Enable Register Address PDR 0xEC0h optional PPCR Port Pull up down Control Register Address PDR 0xF00h optional EPFR PFR 1 Peripheral output PPER EPILR PPCR PDR read Pull Up D...

Page 473: ...uring all ports according to their functional specification input level output drive pull up or pull down resistor etc it is mandatory to globally enable the inputs by setting the port input enable bit GPORTEN 0 The inputs of all ports are disabled 1 The inputs of all ports are enabled CPORTEN 0 The inputs of the bootloader communication ports are disabled 1 The inputs of the bootloader communicat...

Page 474: ...ternal bus mode if external bus is enabled otherwise general purpose port PFR00 4 0 Port is in general purpose port mode 1 Port is in external bus mode if external bus is enabled otherwise general purpose port PFR00 3 0 Port is in general purpose port mode 1 Port is in external bus mode if external bus is enabled otherwise general purpose port PFR00 2 0 Port is in general purpose port mode 1 Port ...

Page 475: ...wise general purpose port PFR01 4 0 Port is in general purpose port mode 1 Port is in external bus mode if external bus is enabled otherwise general purpose port PFR01 3 0 Port is in general purpose port mode 1 Port is in external bus mode if external bus is enabled otherwise general purpose port PFR01 2 0 Port is in general purpose port mode 1 Port is in external bus mode if external bus is enabl...

Page 476: ...ise general purpose port PFR02 4 0 Port is in general purpose port mode 1 Port is in external bus mode if external bus is enabled otherwise general purpose port PFR02 3 0 Port is in general purpose port mode 1 Port is in external bus mode if external bus is enabled otherwise general purpose port PFR02 2 0 Port is in general purpose port mode 1 Port is in external bus mode if external bus is enable...

Page 477: ...ise general purpose port PFR03 4 0 Port is in general purpose port mode 1 Port is in external bus mode if external bus is enabled otherwise general purpose port PFR03 3 0 Port is in general purpose port mode 1 Port is in external bus mode if external bus is enabled otherwise general purpose port PFR03 2 0 Port is in general purpose port mode 1 Port is in external bus mode if external bus is enable...

Page 478: ...rwise general purpose port PFR04 4 0 Port is in general purpose port mode 1 Port is in external bus mode if external bus is enabled otherwise general purpose port PFR04 3 0 Port is in general purpose port mode 1 Port is in external bus mode if external bus is enabled otherwise general purpose port PFR04 2 0 Port is in general purpose port mode 1 Port is in external bus mode if external bus is enab...

Page 479: ...rwise general purpose port PFR05 4 0 Port is in general purpose port mode 1 Port is in external bus mode if external bus is enabled otherwise general purpose port PFR05 3 0 Port is in general purpose port mode 1 Port is in external bus mode if external bus is enabled otherwise general purpose port PFR05 2 0 Port is in general purpose port mode 1 Port is in external bus mode if external bus is enab...

Page 480: ...rwise general purpose port PFR06 4 0 Port is in general purpose port mode 1 Port is in external bus mode if external bus is enabled otherwise general purpose port PFR06 3 0 Port is in general purpose port mode 1 Port is in external bus mode if external bus is enabled otherwise general purpose port PFR06 2 0 Port is in general purpose port mode 1 Port is in external bus mode if external bus is enab...

Page 481: ...wise general purpose port PFR07 4 0 Port is in general purpose port mode 1 Port is in external bus mode if external bus is enabled otherwise general purpose port PFR07 3 0 Port is in general purpose port mode 1 Port is in external bus mode if external bus is enabled otherwise general purpose port PFR07 2 0 Port is in general purpose port mode 1 Port is in external bus mode if external bus is enabl...

Page 482: ...tion is BGRNTX PFR08 4 0 Port is in general purpose port mode 1 Port is in external bus mode if external bus is enabled otherwise general purpose port External bus function is RDX PFR08 3 0 Port is in general purpose port mode 1 Port is in external bus mode if external bus is enabled otherwise general purpose port External bus function is WRX3 PFR08 2 0 Port is in general purpose port mode 1 Port ...

Page 483: ...led otherwise general purpose port PFR09 4 0 Port is in general purpose port mode 1 Port is in external bus mode if external bus is enabled otherwise general purpose port PFR09 3 0 Port is in general purpose port mode 1 Port is in external bus mode if external bus is enabled otherwise general purpose port PFR09 2 0 Port is in general purpose port mode 1 Port is in external bus mode if external bus...

Page 484: ...bled otherwise general purpose port EPFR10 4 0 External bus function is MCLKO 1 External bus function is MCLKO inverted output PFR10 3 0 Port is in general purpose port mode 1 Port is in external bus mode if external bus is enabled otherwise general purpose port External bus function is WEX PFR10 2 0 Port is in general purpose port mode 1 Port is in external bus mode if external bus is enabled oth...

Page 485: ...rwise the port can be used as general purpose port PFR11 1 0 Port is in general purpose port mode 1 Port is in DMA function mode DMA function is IOWRX output PFR11 0 0 Port is in general purpose port mode 1 Port is in DMA function mode DMA function is IORDX output Addr 7 6 5 4 3 2 1 0 initial PFR11 0D8Bh PFR11 1 PFR11 0 00 EPFR11 0DCBh R W R W R W R W R W R W R W R W ...

Page 486: ... mode DMA function is DACKX3 output PFR12 4 0 Port is in general purpose port mode 1 Port is in DMA function mode DMA function is DREQ3 input PFR12 3 0 Port is in general purpose port mode 1 Port is in DMA function mode DMA function is DEOP2 output PFR12 2 0 Port is in general purpose port mode 1 Port is in DMA function mode EPFR12 2 0 DMA function is DEOTX2 input 1 DMA function is DEOP2 output PF...

Page 487: ... mode DMA function is DACKX1 output PFR13 4 0 Port is in general purpose port mode 1 Port is in DMA function mode DMA function is DREQ1 input PFR13 3 0 Port is in general purpose port mode 1 Port is in DMA function mode DMA function is DEOP0 output PFR13 2 0 Port is in general purpose port mode 1 Port is in DMA function mode EPFR13 2 0 DMA function is DEOTX0 input 1 DMA function is DEOP0 output PF...

Page 488: ...function is ICU6 input 1 ICU5 is internally connected to LSYN of LIN UART 5 13 PFR14 4 0 Port is in general purpose port mode 1 Port is in resource function mode Resource function is TIN4 and TTG12 4 input and EPFR14 4 0 Resource function is ICU4 input 1 ICU4 is internally connected to LSYN of LIN UART 4 12 PFR14 3 0 Port is in general purpose port mode 1 Port is in resource function mode Resource...

Page 489: ...source function is ICU1 input 1 ICU1 is internally connected to LSYN of LIN UART 1 9 PFR14 0 0 Port is in general purpose port mode 1 Port is in resource function mode Resource function is TIN0 and TTG8 0 input and EPFR14 0 0 Resource function is ICU0 input 1 ICU0 is internally connected to LSYN of LIN UART 0 8 ...

Page 490: ...rt is in resource function mode EPFR15 4 0 Resource function is OCU4 output 1 Resource function is TOT4 output PFR15 3 0 Port is in general purpose port mode 1 Port is in resource function mode EPFR15 3 0 Resource function is OCU3 output 1 Resource function is TOT3 output PFR15 2 0 Port is in general purpose port mode 1 Port is in resource function mode EPFR15 2 0 Resource function is OCU2 output ...

Page 491: ...esource function mode EPFR16 5 0 Resource function is PPG13 output 1 Resource function is SGO output PFR16 4 0 Port is in general purpose port mode 1 Port is in resource function mode EPFR16 4 0 Resource function is PPG12 output 1 Resource function is SGA output PFR16 3 0 Port is in general purpose port mode 1 Port is in resource function mode Resource function is PPG11 output PFR16 2 0 Port is in...

Page 492: ...ction is PPG5 output PFR17 4 0 Port is in general purpose port mode 1 Port is in resource function mode Resource function is PPG4 output PFR17 3 0 Port is in general purpose port mode 1 Port is in resource function mode Resource function is PPG3 output PFR17 2 0 Port is in general purpose port mode 1 Port is in resource function mode Resource function is PPG2 output PFR17 1 0 Port is in general pu...

Page 493: ...8 5 0 Resource function is SOT7 output 1 Resource function is BIN3 input PFR18 4 0 Port is in general purpose port mode 1 Port is in resource function mode Resource function is SIN7 and AIN3 input PFR18 2 0 Port is in general purpose port mode 1 Port is in resource function mode EPFR18 2 0 Resource function is SCK6 input output 1 Resource function is ZIN2 and CK6 input PFR18 1 0 Port is in general...

Page 494: ...t is in resource function mode Resource function is SOT5 output PFR19 4 0 Port is in general purpose port mode 1 Port is in resource function mode Resource function is SIN5 input PFR19 2 0 Port is in general purpose port mode 1 Port is in resource function mode EPFR19 2 0 Resource function is SCK4 input output 1 Resource function is CK4 input PFR19 1 0 Port is in general purpose port mode 1 Port i...

Page 495: ...0 5 0 Resource function is SOT3 output 1 Resource function is BIN1 input PFR20 4 0 Port is in general purpose port mode 1 Port is in resource function mode Resource function is SIN3 and AIN1 input PFR20 2 0 Port is in general purpose port mode 1 Port is in resource function mode EPFR20 2 0 Resource function is SCK2 input output 1 Resource function is ZIN0 and CK2 input PFR20 1 0 Port is in general...

Page 496: ...t is in resource function mode Resource function is SOT1 output PFR21 4 0 Port is in general purpose port mode 1 Port is in resource function mode Resource function is SIN1 input PFR21 2 0 Port is in general purpose port mode 1 Port is in resource function mode EPFR21 2 0 Resource function is SCK0 input output 1 Resource function is CK0 input PFR21 1 0 Port is in general purpose port mode 1 Port i...

Page 497: ... in general purpose port mode 1 Port is in resource function mode Resource function is SDA0 open drain and INT14 input Remark This pin supports external interrupt wake up from STOP HIZ mode Because of this the internal input line is not forced to low in STOP HIZ mode if the PFR is set to 1 and interrupt is enabled with ENIR1 EN14 set to 1 PFR22 3 0 Port is in general purpose port mode 1 Port is in...

Page 498: ...ecause of this the internal input line is not forced to low in STOP HIZ mode if the PFR is set to 1 and interrupt is enabled with ENIR1 EN12 set to 1 Remark It is generally possible to use input only resource functions like e g INT ICU CAN RX UART SIN also in the Port I O input mode PFR 0 and DDR 0 In that case the internal input line is forced to low in STOP HIZ mode ...

Page 499: ... is in resource function mode Resource function is RX2 input and INT10 input Remark This pin supports external interrupt wake up from STOP HIZ mode Because of this the internal input line is not forced to low in STOP HIZ mode if the PFR is set to 1 and interrupt is enabled with ENIR1 EN10 set to 1 PFR23 3 0 Port is in general purpose port mode 1 Port is in resource function mode Resource function ...

Page 500: ...ecause of this the internal input line is not forced to low in STOP HIZ mode if the PFR is set to 1 and interrupt is enabled with ENIR1 EN8 set to 1 Remark It is generally possible to use input only resource functions like e g INT ICU CAN RX UART SIN also in the Port I O input mode PFR 0 and DDR 0 In that case the internal input line is forced to low in STOP HIZ mode ...

Page 501: ...esource function mode Resource function is SCL2 open drain and INT5 input Remark This pin supports external interrupt wake up from STOP HIZ mode Because of this the internal input line is not forced to low in STOP HIZ mode if the PFR is set to 1 and interrupt is enabled with ENIR0 EN5 set to 1 PFR24 4 0 Port is in general purpose port mode 1 Port is in resource function mode Resource function is S...

Page 502: ...rnal input line is not forced to low in STOP HIZ mode if the PFR is set to 1 and interrupt is enabled with ENIR0 EN1 set to 1 PFR24 0 0 Port is in general purpose port mode 1 Port is in resource function mode Resource function is INT0 input Remark This pin supports external interrupt wake up from STOP HIZ mode Because of this the internal input line is not forced to low in STOP HIZ mode if the PFR...

Page 503: ...CMP5 input if selected PFR25 4 0 Port is in general purpose port mode 1 Port is in resource function mode Resource function is SMC1P5 output CMP5 input if selected PFR25 3 0 Port is in general purpose port mode 1 Port is in resource function mode Resource function is SMC2M4 output CMP4 input if selected PFR25 2 0 Port is in general purpose port mode 1 Port is in resource function mode Resource fun...

Page 504: ... Port is in resource function mode EPFR26 4 0 Resource function is SMC1P3 output CMP3 and or AN28 input if selected 1 Resource function is AN28 input PFR26 3 0 Port is in general purpose port mode 1 Port is in resource function mode EPFR26 3 0 Resource function is SMC2M2 output CMP2 and or AN27 input if selected 1 Resource function is AN27 input PFR26 2 0 Port is in general purpose port mode 1 Por...

Page 505: ... Port is in resource function mode EPFR27 4 0 Resource function is SMC1P1 output CMP1 and or AN20 input if selected 1 Resource function is AN20 input PFR27 3 0 Port is in general purpose port mode 1 Port is in resource function mode EPFR27 3 0 Resource function is SMC2M0 output CMP0 and or AN19 input if selected 1 Resource function is AN19 input PFR27 2 0 Port is in general purpose port mode 1 Por...

Page 506: ...eneral purpose port mode 1 Port is in resource function mode Resource function is AN13 input PFR28 4 0 Port is in general purpose port mode 1 Port is in resource function mode Resource function is AN12 input PFR28 3 0 Port is in general purpose port mode 1 Port is in resource function mode Resource function is AN11 input PFR28 2 0 Port is in general purpose port mode 1 Port is in resource function...

Page 507: ...ction is AN5 input PFR29 4 0 Port is in general purpose port mode 1 Port is in resource function mode Resource function is AN4 input PFR29 3 0 Port is in general purpose port mode 1 Port is in resource function mode Resource function is AN3 input PFR29 2 0 Port is in general purpose port mode 1 Port is in resource function mode Resource function is AN2 input PFR29 1 0 Port is in general purpose po...

Page 508: ...ce function mode Resource function is V1 input PFR30 4 0 Port is in general purpose port mode 1 Port is in resource function mode Resource function is V0 input PFR30 3 0 Port is in general purpose port mode 1 Port is in resource function mode Resource function is COM3 output PFR30 2 0 Port is in general purpose port mode 1 Port is in resource function mode Resource function is COM2 output PFR30 1 ...

Page 509: ...tion is SEG37 output PFR31 4 0 Port is in general purpose port mode 1 Port is in resource function mode Resource function is SEG36 output PFR31 3 0 Port is in general purpose port mode 1 Port is in resource function mode Resource function is SEG35 output PFR31 2 0 Port is in general purpose port mode 1 Port is in resource function mode Resource function is SEG34 output PFR31 1 0 Port is in general...

Page 510: ...rt is in general purpose port mode 1 Port is in resource function mode EPFR32 4 0 Resource function is SEG28 output 1 Resource function is SIN15 input PFR32 3 0 Port is in general purpose port mode 1 Port is in resource function mode Resource function is SEG27 output PFR32 2 0 Port is in general purpose port mode 1 Port is in resource function mode EPFR32 2 0 Resource function is SEG26 output 1 Re...

Page 511: ...rt is in general purpose port mode 1 Port is in resource function mode EPFR33 4 0 Resource function is SEG20 output 1 Resource function is SIN13 input PFR33 3 0 Port is in general purpose port mode 1 Port is in resource function mode Resource function is SEG19 output PFR33 2 0 Port is in general purpose port mode 1 Port is in resource function mode EPFR33 2 0 Resource function is SEG18 output 1 Re...

Page 512: ...rt is in general purpose port mode 1 Port is in resource function mode EPFR34 4 0 Resource function is SEG12 output 1 Resource function is SIN11 input PFR34 3 0 Port is in general purpose port mode 1 Port is in resource function mode Resource function is SEG11 output PFR34 2 0 Port is in general purpose port mode 1 Port is in resource function mode EPFR34 2 0 Resource function is SEG10 output 1 Re...

Page 513: ...rt is in general purpose port mode 1 Port is in resource function mode EPFR35 4 0 Resource function is SEG4 output 1 Resource function is SIN9 input PFR35 3 0 Port is in general purpose port mode 1 Port is in resource function mode Resource function is SEG3 output PFR35 2 0 Port is in general purpose port mode 1 Port is in resource function mode EPFR35 2 0 Resource function is SEG2 output 1 Resour...

Page 514: ...2 PILR05 1 PILR05 0 0000 0000 PILR06 0E46h PILR06 7 PILR06 6 PILR06 5 PILR06 4 PILR06 3 PILR06 2 PILR06 1 PILR06 0 0000 0000 PILR07 0E47h PILR07 7 PILR07 6 PILR07 5 PILR07 4 PILR07 3 PILR07 2 PILR07 1 PILR07 0 0000 0000 PILR08 0E48h PILR08 7 PILR08 6 PILR08 5 PILR08 4 PILR08 3 PILR08 2 PILR08 1 PILR08 0 0000 0000 PILR09 0E49h PILR09 7 PILR09 6 PILR09 5 PILR09 4 PILR09 3 PILR09 2 PILR09 1 PILR09 0 ...

Page 515: ...PILR34 0 0000 0000 PILR35 0E63h PILR35 7 PILR35 6 PILR35 5 PILR35 4 PILR35 3 PILR35 2 PILR35 1 PILR35 0 0000 0000 R W R W R W R W R W R W R W R W Addr 7 6 5 4 3 2 1 0 initial EPILR00 0E80h EPILR00 7 EPILR00 6 EPILR00 5 EPILR00 4 EPILR00 3 EPILR00 2 EPILR00 1 EPILR00 0 0000 0000 EPILR01 0E81h EPILR01 7 EPILR01 6 EPILR01 5 EPILR01 4 EPILR01 3 EPILR01 2 EPILR01 1 EPILR01 0 0000 0000 EPILR02 0E82h EPI...

Page 516: ... EPILR16 0E90h EPILR17 0E91h EPILR18 0E92h EPILR19 0E93h EPILR20 0E94h EPILR21 0E95h EPILR22 0E96h EPILR23 0E97h EPILR24 0E98h EPILR25 0E99h EPILR26 0E9Ah EPILR27 0E9Bh EPILR28 0E9Ch EPILR29 0E9Dh EPILR30 0E9Eh EPILR31 0E9Fh EPILR32 0EA0h EPILR33 0EA1h EPILR34 0EA2h EPILR35 0EA3h R W R W R W R W R W R W R W R W Bit Port Pull Up Pull Down Enable Registers 0 default 1 PPERx y Pull Up Pull Down disab...

Page 517: ...17 0 0000 0000 PPER18 0ED2h PPER18 7 PPER18 6 PPER18 5 PPER18 4 PPER18 3 PPER18 2 PPER18 1 PPER18 0 0000 0000 PPER19 0ED3h PPER19 7 PPER19 6 PPER19 5 PPER19 4 PPER19 3 PPER19 2 PPER19 1 PPER19 0 0000 0000 PPER20 0ED4h PPER20 7 PPER20 6 PPER20 5 PPER20 4 PPER20 3 PPER20 2 PPER20 1 PPER20 0 0000 0000 PPER21 0ED5h PPER21 7 PPER21 6 PPER21 5 PPER21 4 PPER21 3 PPER21 2 PPER21 1 PPER21 0 0000 0000 PPER2...

Page 518: ...111 PPCR12 0F0Ch PPCR12 7 PPCR12 6 PPCR12 5 PPCR12 4 PPCR12 3 PPCR12 2 PPCR12 1 PPCR12 0 1111 1111 PPCR13 0F0Dh PPCR13 7 PPCR13 6 PPCR13 5 PPCR13 4 PPCR13 3 PPCR13 2 PPCR13 1 PPCR13 0 1111 1111 PPCR14 0F0Eh PPCR14 7 PPCR14 6 PPCR14 5 PPCR14 4 PPCR14 3 PPCR14 2 PPCR14 1 PPCR14 0 1111 1111 PPCR15 0F0Fh PPCR15 7 PPCR15 6 PPCR15 5 PPCR15 4 PPCR15 3 PPCR15 2 PPCR15 1 PPCR15 0 1111 1111 PPCR16 0F10h PPC...

Page 519: ...ODRx y 5 mA output drive 2 mA output drive Addr 7 6 5 4 3 2 1 0 initial PODR00 0E00h PODR00 7 PODR00 6 PODR00 5 PODR00 4 PODR00 3 PODR00 2 PODR00 1 PODR00 0 0000 0000 PODR01 0E01h PODR01 7 PODR01 6 PODR01 5 PODR01 4 PODR01 3 PODR01 2 PODR01 1 PODR01 0 0000 0000 PODR02 0E02h PODR02 7 PODR02 6 PODR02 5 PODR02 4 PODR02 3 PODR02 2 PODR02 1 PODR02 0 0000 0000 PODR03 0E03h PODR03 7 PODR03 6 PODR03 5 POD...

Page 520: ...23 0 0000 0000 PODR24 0E18h PODR24 7 PODR24 6 PODR24 5 PODR24 4 PODR24 3 PODR24 2 PODR24 1 PODR24 0 0000 0000 PODR25 0E19h PODR25 7 PODR25 6 PODR25 5 PODR25 4 PODR25 3 PODR25 2 PODR25 1 PODR25 0 0000 0000 PODR26 0E1Ah PODR26 7 PODR26 6 PODR26 5 PODR26 4 PODR26 3 PODR26 2 PODR26 1 PODR26 0 0000 0000 PODR27 0E1Bh PODR27 7 PODR27 6 PODR27 5 PODR27 4 PODR27 3 PODR27 2 PODR27 1 PODR27 0 0000 0000 PODR2...

Page 521: ...505 Chapter 30 I O Ports 3 Port Register Settings ...

Page 522: ...506 Chapter 30 I O Ports 3 Port Register Settings ...

Page 523: ...ach bank can be output The size of each area can be set in multiples of 64 KB 64 KB to 2 GB for each chip select area An area can be set at any location in the logical address space Boundaries may be limited depending on the size of the area In each chip select area the following functions can be set independently Enabling and disabling of the chip select area Disabled areas cannot be accessed Set...

Page 524: ... by DMA can be performed Transfer between memory and I O can be performed in a single access operation The memory wait cycle can be synchronized with the I O wait cycle in fly by transfer The hold time can be secured by only extending transfer source access Idle recovery cycles specific to fly by transfer can be set External bus arbitration using BRQ and BGRNT can be performed Pins that are not us...

Page 525: ...s Internal data bus write buffer switch switch read buffer ADDRESS BLOCK DATA BLOCK 1 or 2 address buffer ASZ ASR BRQ BGRNT RDY RD WR0 WR1 WR2 WR3 AS BAA SRAS SCAS SWE MCLKE DQMUU DQMUL DQMLU DQMLL CS0 CS7 MUX all block control registers control comparator SDRAM control RCR refresh counter underflow External data bus External address bus External terminal controller ...

Page 526: ...0 AD15 to AD00 CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 AS SYSCLK MCLK RD WR WR0 UUB WR1 ULB WR2 ULB WR3 ULB RDY BRQ BGRNT Memory interface MCLK MCLKE MCLKI for SDRAM LBA AS BAA for burst ROM FLASH SRAS SCAS SWE WR for SDRAM DQMUU DQMUL DQMLU DQMLL for SDRAM WR0 WR1 WR2 WR3 DMA interface IOWR IORD DACK0 DACK1 DREQ0 DREQ1 DEOP0 DEOP1 1 4 Register List Figure 1 2 List of External Bus Interface Registers show...

Page 527: ... Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved IOWR3 Reserved TCR Reserved Reserved Reserved Reserved Reserved MCRB Reserved IOWR1 Reserved CHER Reserved Reserved Reserved Reserved MODR Reserved Reserved Reserved Reserved 1 Reserved indicates a reserved register Be sure to set 0 2 MODR cannot be accessed from user programs 00000640H 00000644H 00000648H 0000064cH 00000650H...

Page 528: ...n register MCRB for FCRAM auto precharge ON mode I O wait registers for DMAC IOWR0 3 Chip select enable register CSER Cache enable register CHER Pin timing control register TCR Mode register MODR 2 1 Area Select Registers 0 7 ASR0 7 This section explains the configuration and functions of area select registers 0 7 ASR0 7 Configuration of area select registers 0 7 ASR0 7 The area select registers A...

Page 529: ...set the corresponding ASR register before enabling each chip select area with the CSER register 2 2 Area Configuration Registers 0 7 ACR0 7 This section explains the configuration and functions of area configuration registers 0 7 ACR0 7 Configuration of Area Configuration Registers 0 7 ACR0 7 The area configuration registers 0 7 ACR0 7 FArea Configuration Register 0 7 set the function of each chip...

Page 530: ... 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 00000643H SREN PFEN WREN 0 TYP3 TYP2 TYP1 TYP0 W R ACR1H 00000646H ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 W R ACR1L 00000647H SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 xxxxxxxxB XxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB XxxxxxxxB xxxxxxxxB W R ACR2H 0000064AH ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 W R ACR2L 0000064BH SREN PFEN WREN LEND TY...

Page 531: ...0400000H byte ASR A 31 22 bits are valid ACR4H 15 14 13 12 11 10 9 8 15 14 13 12 11 10 9 8 15 14 13 12 11 10 9 8 15 14 13 12 11 10 9 8 00000652H ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 ACR4L ACR5H ACR5L ACR6H ACR6L ACR7H ACR7L 7 6 5 4 3 2 1 0 00000653H SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 00000656H ASZ3 ASZ2 ASZ1 ASZ0 DBW1DBW0 BST1 BST0 7 6 5 4 3 2 1 0 00000657H SREN PFEN WREN LEND TYP3 TYP2 TY...

Page 532: ...T1 0 Burst Size 1 0 These bits set the maximum burst length of each chip select area as indicated in Table 2 3 Setting of the Maximum Burst Length of Each Chip Select 0 1 1 1 8 MB 00800000H byte ASR A 31 23 bits are valid 1 0 0 0 16 MB 01000000H byte ASR A 31 24 bits are valid 1 0 0 1 32 MB 02000000H byte ASR A 31 25 bits are valid 1 0 1 0 64 MB 04000000H byte ASR A 31 26 bits are valid 1 0 1 1 12...

Page 533: ...trobe output AS BAA RD WR0 WR1 WR2 WR3 WR MCLK MCLKE is set to high impedance only if sharing of all areas enabled by CSER is enabled Bit 6 PFEN PreFetch Enable This bit sets enabling and disabling of prefetching of each chip select area as indicated in the following table When reading from an area for which prefetching is enabled the subsequent address is read in advance and stored in the built i...

Page 534: ...lect area as indicated in Table 2 4 Access Type Settings for Each Chip Select Area 1 Enable write LEND Order of bytes 0 Big endian 1 Little endian Table 2 4 Access Type Settings for Each Chip Select Area TYP3 TYP2 TYP1 TYP0 Access type 0 0 x x Normal access asynchronous SRAM I O and single page burst ROM FLASH 0 1 x x Address data multiplex access 8 16 bit bus width only 0 x x 0 Disable WAIT inser...

Page 535: ...setting For the following ACR setting the setting on the base setting area side is valid Bits 3 0 TYPE3 0 Access type setting For the AWR settings the settings on the mask setting area side are valid For the CHER settings the settings on the mask setting area side are valid A mask setting area can be set for only part of another CS area base setting area You cannot set a mask setting area for an a...

Page 536: ...9 W08 01111111b 01111111b 11111011B 11111011B W R AWR0L AWR1L 23 22 21 20 19 18 17 16 23 22 21 20 19 18 17 16 23 22 21 20 19 18 17 16 00000661H W07 W06 W05 W04 W03 W02 W01 W00 W R AWR1H 00000662H W15 W14 W13 W12 W11 W10 W09 W08 xxxxxxxxb xxxxxxxxb xxxxxxxxb xxxxxxxxb xxxxxxxxb xxxxxxxxb xxxxxxxxb xxxxxxxxb xxxxxxxxb xxxxxxxxb xxxxxxxxb xxxxxxxxb xxxxxxxxb xxxxxxxxb xxxxxxxxb xxxxxxxxb W R 7 6 5 4 ...

Page 537: ...ctions of the bits in the area wait registers AWR0 7 TYP3 TYP2 TYP1 TYP0 Access type 0 0 x x Normal access asynchronous SRAM I O and single page burst ROM FLASH 0 1 x x Address data multiplex access 8 16 bit bus width only 0000066AH W15 W14 W13 W12 W11 W10 W09 W08 AWR5L 7 6 5 4 3 2 1 0 0000066BH W07 W06 W05 W04 W03 W02 W01 W00 31 30 29 28 27 26 25 24 0000066CH W15 W14 W13 W12 W11 W10 W09 W08 00000...

Page 538: ...only for burst cycles Table 2 6 Settings for the Number of Auto Wait Cycles During Burst Access lists the settings for the number of auto wait cycles during burst access If the same value is set for the first access wait cycle and inpage access wait cycle the access time for the address in each access cycle is not the same This is because the inpage access cycle contains an address output delay Ta...

Page 539: ... idle cycles Bits 5 4 W05 W04 Write Recovery Cycle The write recovery cycle is set if a device that limits the access period after write access is to be controlled During a write recovery cycle all chip select signals are negated and the data pins maintain the high impedance state If the write recovery cycle is set to 1 or more a write recovery cycle is always inserted after write access Table 2 8...

Page 540: ... in the clock cycle following the cycle in which synchronous write enable output is asserted If write data cannot be output because the internal bus is temporarily unavailable assertion of synchronous write enable output may be extended until write data can be output Read strobe output RD functions as an asynchronous read strobe regardless of the setting of the WR0 WR3 and WRn output timing Use it...

Page 541: ...DACK signal basic mode output to the same area in the same way DACK output in basic mode has the same waveforms as those of CS output to the same area Bits 1 W01 CSn RD WRn Setup Extension Cycle The CSn RD WRn setup extension cycle is set to extend the period before the read write strobe is asserted after CSn is asserted At least one setup extension cycle is inserted before the read write strobe i...

Page 542: ...type TYP3 to TYP0 bits in the ACR6 and ACR7 registers has been set as in Table 1 2 18 serve for SDRAM FCRAM access Table 1 2 18 lists the access type settings TYP3 to TYP0 bits The following explains those functions of individual bits in AWR6 and AWR7 which apply to SDRAM access areas As the initial value is undefined set the access type before each area is enabled by the chip select area enable r...

Page 543: ...t the minimum number of cycles taken until issuance Table 4 2 21 lists the settings for the read to write cycle For all the areas connected to SDRAM FCRAM set these bits to the same read to write cycle The number of read to write idle cycles is one smaller than the number of cycles set by this bit Bits 5 4 W05 and W04 Write Recovery Cycle Write recovery cycle Set these bits to the minimum number o...

Page 544: ...s Set these bits to the number of RAS precharge cycles Table 4 2 24 lists the settings for the RAS precharge cycle For all the areas connected to SDRAM FCRAM set these bits to the same RAS precharge cycle 2 4 Memory setting register MCRA for SDRAM FCRAM auto precharge OFF mode This section describes the configuration and the function of memory setting register MCRA for SDRAM FCRAM auto precharge O...

Page 545: ...CRA Updating the MCRA therefore updates the MCRB accordingly The following summarizes the functions of individual bits in the memory setting register MCRA for SDRAM FCRAM auto precharge OFF mode Bit 31 Reserved bit Be sure to set this bit to 0 Bits 30 28 PSZ2 PSZ1 PSZ0 Page SiZe Page size Set these bits to the page size of SDRAM to be connected Table 2 26 lists the settings for the page size of SD...

Page 546: ...RAM auto precharge ON mode This section describes the memory setting register MCRB for FCRAM auto precharge ON mode Structure of the Memory Setting Register MCRB for FCRAM auto precharge ON mode Settings for Memory configuration register MCRB Memory Configuration Register for extend type B for FCRAM auto precharge ON mode is used to make various settings for FCRAM connected to the chip select area...

Page 547: ...DMAC IOWR0 3 The I O wait registers for DMAC IOWR0 3 I O Wait Register for DMAC 0 3 set various kinds of waits during DMA fly by access Figure 2 6 Configuration of the I O wait registers for DMAC IOWR0 1 2 3 shows the configuration of the I O wait registers for DMAC IOWR0 3 Figure 2 6 Configuration of the I O Wait Registers for DMAC IOWR0 3 Table 2 21 Access type settings TYP3 to TYP0 bits TYP3 TY...

Page 548: ...s side during DMA fly by access If 0 is set the read strobe signal RD for memory I O and IORD for I O memory and the write strobe signal IOWR for memory I O and WR0 WR3 and WR for I O memory on the transfer source access side are output at the same timing If 1 is set the read strobe signal is output one cycle longer than the write strobe signal to secure a hold time for data at the transfer source...

Page 549: ...533 Chapter 31 External Bus 2 External Bus Interface Registers is set to the high impedance state ...

Page 550: ...les to be inserted Consequently more wait cycles than specified by the IWnn bits may be inserted Configuration of the Chip Select Enable Register CSER The chip select enable register CSER Chip Select Enable register enables and disables each chip select area Figure 2 7 Configuration of the Chip Select Enable Register CSER shows the configuration of the chip select enable register CSER Figure 2 7 C...

Page 551: ... of data read from each chip select area Figure 2 8 Configuration of the Cache Enable Register CHER shows the configuration of the cache enable register CHER Figure 2 8 Configuration of the Cache Enable Register CHER Functions of Bits in the Cache Enable Register CHER The following explains the functions of the bits in the cache enable register CHER CSE7 0 Area control 0 Disable 1 Enable Table 2 2...

Page 552: ... 9 Configuration of the Pin Timing Control Register TCR Functions of Bits in the Pin Timing Control Register TCR The following explains the functions of the bits in the pin timing control register TCR Bit 7 BREN BRQ Enable This bit enables BRQ pin input and external bus sharing In the initial state 0 BRQ input is ignored When 1 is set the bus is made open control with high impedance and BGRNT is a...

Page 553: ...are retained unchanged The settings for idle cycles recovery cycles setup and hold cycles are not affected Table 2 25 Settings for Wait Cycle Reduction lists the settings for the wait cycle reduction for combinations of these bits The purpose of this function is to prevent an excessive access cycle wait during operation on a low speed clock for example when the base clock is switched to low speed ...

Page 554: ...g 0 terminates the self refresh mode To hold the contents of SDRAM when putting the LSI into stop mode use this bit to enter the self refresh mode before entering the stop mode At this time centralized refreshing is performed before transition to the self refresh mode External access requests generated before it is completed are put on hold The mode transits to the stop mode The device is released...

Page 555: ...NT0 ReFresh INTerval Auto refresh interval Set these bits to the interval for automatic refreshing The auto refresh interval can be obtained for distributed refresh mode REFINT5 REFINT0 value x 32 x external bus clock cycle or for centralized refresh mode REFINT5 REFINT0 value x 32 x RFC specified number of times x external bus clock cycle Calculate the design value in consideration of the maximum...

Page 556: ...tion of power on control Writing 1 to the PON bit starts the SDRAM power on sequence Before starting the power on sequence be sure to set the relevant registers such as AWR MCRA B and CSER This bit returns to 0 as soon as the power on sequence is started When enabling the PON bit set RFINT and enable RRLD to activate the refresh counter Refreshing is not performed only with the PON bit Do not enab...

Page 557: ...ternal Bus Interface Registers Table 4 2 47 lists the settings for the refresh cycle tRC Table 2 31 Settings for the refresh cycle tRC TRC2 TRC1 TRC0 Refresh cycle tRC 0 0 0 4 0 0 1 5 0 1 0 6 0 1 1 7 1 0 0 8 1 0 1 9 1 1 0 10 1 1 1 11 ...

Page 558: ...3 0 ASR1 0003H ACR1 ASZ3 0 0000B Chip select area 1 is assigned to 00030000H to 0003FFFFH ASR2 0FFCH ACR2 ASZ3 0 0010B Chip select area 2 is assigned to 0FFC0000H to 10000000H ASR3 0011H ACR3 SZ3 0 0100B Chip select area 3 is assigned to 00100000H to 00200000H Since at this point 1 MB is set for bits ASZ3 0 of the ACR the unit for boundaries 1 MB and bits 19 16 of ASR3 are ignored Before there is ...

Page 559: ...n the data bus used according to the specified data bus width and the corresponding control signal for each bus mode Ordinary bus interface Figure 4 1 Data Bus Width and Control Signal on the Ordinary Bus Interface Time division I O interface Figure 4 2 Data Bus Width and Control Signal in the Time Division I O Interface D31 D0 a 32 bit bus width data bus Control signal WR0 UUB WR1 ULB WR2 LUB WR3...

Page 560: ...e MB91460 series is normally big endian and performs external bus access Data Format The relationship between the internal register and the external data bus is as follows Word access when LD ST instruction executed Figure 4 4 Relationship between Internal Register and External Data Bus for Word Access D31 D0 a 32 bit bus width Data bus Control signal DQMUU DQMUL DQMLU DQMLL Data bus Control signa...

Page 561: ... address low order b Output address low order digits 00 digits 10 Internal register External bus Internal register External bus D31 D15 D23 D7 D0 AA D31 D15 D23 D7 D0 AA D31 D15 D23 D7 D0 AA D31 D15 D23 D7 D0 AA D31 D15 D23 D7 D0 AA D31 D15 D23 D7 D0 AA D31 D15 D23 D7 D0 AA D31 D15 D23 D7 D0 AA a Output address b Output address c Output address d Output address low order digits 00 low order digits...

Page 562: ...us Width and Figure 4 12 External Bus Access for 8 Bit Bus Width Access byte location Program address and output address Bus access count The MB91460 series does not detect misalignment errors Therefore for word access the lower two bits of the output address are always 00 regardless of whether 00 01 10 or 11 is specified as the lower two bits by the program For halfword access the lower two bits ...

Page 563: ...1 00 11 10 01 00 11 10 01 00 a PA1 PA0 00 1 Output A1 A0 00 2 Output A1 A0 10 b PA1 PA0 01 1 Output A1 A0 00 2 Output A1 A0 10 c PA1 PA0 10 1 Output A1 A0 00 2 Output A1 A0 10 d PA1 PA0 11 1 Output A1 A0 00 2 Output A1 A0 10 11 10 00 11 10 01 10 01 00 11 01 00 a PA1 PA0 00 1 Output A1 A0 00 b PA1 PA0 01 1 Output A1 A0 00 c PA1 PA0 10 1 Output A1 A0 00 d PA1 PA0 11 1 Output A1 A0 00 1 1 1 1 11 10 0...

Page 564: ...3 4 1 2 3 4 1 2 3 4 1 2 3 4 8bit 00 11 10 01 00 11 10 01 00 11 10 01 00 a PA1 PA0 00 1 Output A1 A0 00 2 Output A1 A0 01 3 Output 1 A0 10 4 Output 1 A0 11 b PA1 PA0 01 1 Output A1 A0 00 2 Output A1 A0 01 3 Output 1 A0 10 4 Output 1 A0 11 c PA1 PA0 10 1 Output A1 A0 00 2 Output A1 A0 01 3 Output 1 A0 10 4 Output 1 A0 11 d PA1 PA0 11 1 Output A1 A0 00 2 Output A1 A0 01 3 Output 1 A0 10 4 Output 1 A0...

Page 565: ... separate Differences between Little Endian and Big Endian The following explains the differences between little endian and big endian The order of addresses that are output is the same for little endian and big endian The data bus control signal used for 32 16 8 bit bus width is the same for little endian and big endian Word access The byte data on the MSB side for big endian address 00 becomes b...

Page 566: ...reason is hardware restrictions related to the endian conversion mechanism Do not place any instruction code in a little endian area Data Format The relationship between the internal register and external data bus is as follows Figure 4 14 Relationship between the Internal Register and External Data Bus for Word Access Figure 4 15 Relationship between Internal Register and External Data Bus for Ha...

Page 567: ...D0 AA D31 D15 D23 D7 D0 AA D31 D15 D23 D7 D0 AA D31 D15 D23 D7 D0 AA D31 D15 D23 D7 D0 AA D31 D15 D23 D7 D0 AA D31 D15 D23 D7 D0 AA D31 D15 D23 D7 D0 AA 3 Halfword access when executing the LDUB STB instructions a Output address b Output address c Output address d Output address low orderdigits 00 low order digits 01 low order digits 10 low order digits 11 Internal External Internal External Inter...

Page 568: ...ng the MB91460 series to external devices for each bus width 32 bit bus width Figure 4 20 Example of Connecting the MB91460 Series to External Devices 32 Bit Bus Width D07 D15 D23 D31 D31 00 01 AA BB CC DD CC DD 10 11 AA BB read write External bus Internal register Output address low order digits D31 D08D07 D00 D16D15 D31 D00 D16D15 D24D23 D08D07 D24D23 This LSI D31 D24 D23 D16 D15 D08 D07 D00 00 ...

Page 569: ...External Devices 16 Bit Bus Width 8 bit bus width Figure 4 22 Example of Connecting the MB91460 Series to External Devices 8 Bit Bus Width big endian area This LSI D31 to D24 D23 to D16 D00 D15 D08 D07 0 1 little endian area D00 D15 D08 D07 0 1 WR0 WR1 D00 D07 D00 D07 big endian area This LSI D31 to D24 little endian area WR0 ...

Page 570: ... Endian and Bus Access 4 3 Comparison of Big Endian and Little Endian External Access This section shows a comparison of big endian and little endian external access in word access halfword access and byte access for each bus width ...

Page 571: ...BB CC AA address 0 Internal External Control Reg terminal terminal address 0 2 D00 D31 D31 AA CC BB DD WR0 WR1 AA CC BB DD Internal External Control Reg terminal terminal 1 2 D16 AA CC BB DD WR0 WR1 DD BB CC AA D1 6 address 0 2 Internal External Control Reg terminal terminal D00 D31 D31 D16 1 2 0 1 2 3 AA AA BB CC DD CC BB DD WR0 1 2 3 4 address Internal External Control Reg terminal terminal D00 ...

Page 572: ...AA D00 address 0 Internal External Control Reg terminal terminal 1 D00 D31 D31 AA BB WR0 WR1 BB AA D00 address 0 Internal External Control Reg terminal terminal 1 D00 D31 D31 CC DD WR2 WR3 DD CC D00 address 2 Internal External Control Reg terminal terminal 1 D00 D31 D31 CC DD WR2 WR3 DD CC D00 address 2 Internal External Control Reg terminal terminal ...

Page 573: ...1 Internal External Control Reg terminal terminal 1 D16 CC DD WR0 WR1 DD CC address 2 D00 D31 D31 Internal External Control Reg terminal terminal 1 D16 AA BB WR0 BB AA address 0 1 D00 D00 D31 D31 Internal External Control Reg terminal terminal 1 2 D24 AA BB WR0 AA BB address 0 1 D00 D00 D31 D31 Internal External Control Reg terminal terminal 1 2 D24 CC DD WR0 DD CC address 2 3 D00 D00 D31 D31 Inte...

Page 574: ...558 Chapter 31 External Bus 4 Endian and Bus Access Byte Access ...

Page 575: ... WR1 D00 address 1 Internal External Control Reg terminal terminal BB BB 1 D00 D31 D31 WR1 D00 address 1 Internal External Control Reg terminal terminal CC CC 1 D00 D31 D31 WR2 D00 address 2 Internal External Control Reg terminal terminal CC CC 1 D00 D31 D31 WR2 D00 address 2 Internal External Control Reg terminal terminal DD DD 1 D00 D31 D31 WR3 D00 address 3 Internal External Control Reg termina...

Page 576: ... D00 D31 D31 Internal External Control Reg terminal terminal 1 D16 BB BB WR1 address 1 D00 D31 D31 Internal External Control Reg terminal terminal 1 D16 CC CC WR0 address 2 D00 D31 D31 Internal External Control Reg terminal terminal 1 D16 CC CC WR0 address 2 D00 D31 D31 Internal External Control Reg terminal terminal 1 D16 DD DD WR1 address 3 D00 D31 D31 Internal External Control Reg terminal term...

Page 577: ... D00 D31 D31 Internal External Control Reg terminal terminal 1 D24 BB BB WR0 address 1 D00 D31 D31 Internal External Control Reg terminal terminal 1 D24 CC CC WR0 address 2 D00 D31 D31 Internal External Control Reg terminal terminal 1 D24 CC CC WR0 address 2 D00 D31 D31 Internal External Control Reg terminal terminal 1 D24 DD DD WR0 address 3 D00 D31 D31 Internal External Control Reg terminal term...

Page 578: ...ary bus interface are explained below with the use of a timing chart Basic timing for successive accesses WRn byte control type Read write Write write Auto wait cycle External wait cycle Synchronous write enable output CSn delay setting CSn RD WRn setup RD WE CSn hold setting DMA fly by transfer I O memory DMA fly by transfer memory I O 5 1 Basic Timing This section shows the basic timing for succ...

Page 579: ...wait cycle of bits W15 W12 of the AWR register is inserted The timing of asserting RD and WR0 WR3 can be delayed by one cycle by setting the W01 bit of the AWR register to 1 However depending on the internal state the assertion of WR0 WR3 may not start in the 2nd cycle and may even be delayed if the W01 bit is set to 0 If a setting is made so that WR0 WR3 is used like TYP3 0 0x0xB WRn is always H ...

Page 580: ...he same as that for WR0 WR3 described in 5 1 Basic Timing WR0 WR3 indicate the byte location expressed with negative logic when they are used for access as the byte enable signal Assertion continues from the bus access start cycle to the bus access end cycle and changes at the same timing as the address timing The byte location for access is indicated for both read access and write access For writ...

Page 581: ...te Setting of the W07 W06 bits of the AWR register enables 0 3 idle cycles to be inserted Settings in the CS area on the read side are enabled This idle cycle is inserted if the next access after a read access is write access or access to another area 5 4 Write Write Operation This section shows the operation timing for write write Write Write Operation Figure 5 4 Timing Chart for the Write Write ...

Page 582: ...cycles recovery cycles are generated Write recovery cycles are also generated if write access is divided into phases for access with a bus width wider than that specified 5 5 Auto Wait Cycle This section shows the operation timing for the auto wait cycle Auto Wait Cycle Timing Figure 5 5 Timing Chart for the Auto Wait Cycle shows the operation timing for TYP3 0 0000B AWR 2008H Write Write Write re...

Page 583: ...ng a total of four cycles for access If auto wait is set the minimum number of bus cycles is 2 cycles first wait cycles For a write operation the minimum number of bus cycles may be still longer depending on the internal state 5 6 External Wait Cycle This section shows the operation timing for the external wait cycle External Wait Cycle Timing Figure 5 6 Timing Chart for the External Wait Cycle sh...

Page 584: ...ect The value at the RDY input pin is evaluated from the last automatic wait cycle on Once a wait cycle is completed the value at the PDY input pin remains invalid until the next access cycle is started 5 7 Synchronous Write Enable Output This section shows the operation timing for synchronous write enable output Operation Timing for Synchronous Write Enable Output Figure 5 7 Timing Chart for Sync...

Page 585: ...For a read from an external bus the synchronous write enable output is H Write data is output from the external data output pin in the clock cycle following the cycle in which synchronous write enable output is asserted If write data cannot be output because the internal bus is temporarily unavailable assertion of synchronous write enable output may be extended until write data can be output Read ...

Page 586: ...meaningless Multiplex bus setting Always write 0 to the TYPE2 bit of ACR RDY input enable setting Always write 0 to the TYPE0 bit of ACR Always set the burst length to 1 BST1 to 0 bit 0 for the synchronous write enable output 5 8 CSn Delay Setting This section shows the operation timing for the CSn delay setting Operation Timing for the CS Delay Setting Figure 5 8 Operation Timing Chart for the CS...

Page 587: ...assertion and read write strobe Setting 1 for the W00 bit of the AWR register enables the RD WRn CSn hold delay to be set Set this bit to extend the period between read write strobe negation and chip select negation The CSn RD WRn setup delay W01 bit and RD WRn CSn hold delay W00 bit can be set independently When making successive accesses within the same chip select area without negating the chip...

Page 588: ...f the IOWR0 3 registers enables 0 15 wait cycles to be inserted If wait is also set on the memory side AWR15 12 is not 0 the larger value is used as the wait cycle after comparison with the I O wait IW3 0 bits 5 11 DMA Fly By Transfer Memory I O This section shows the operation timing for DMA fly by transfer memory I O Operation Timing for DMA Fly By Transfer Memory I O Figure 5 11 Timing Chart fo...

Page 589: ...covery cycles to be inserted If the write recovery cycle is set to 1 or more a write recovery cycle is always inserted after write access Setting bits IW3 0 of the IOWR0 3 registers enables 0 15 wait cycles to be inserted If wait is also set on the memory side AWR15 12 is not 0 the larger value is used as the wait cycle after comparison with the I O wait IW3 0 bits RD IOWR MCLK AS CSn D 31 0 A 31 ...

Page 590: ...h as page mode ROM and burst flash memory is read burst cycles can also be used for reading from normal asynchronous memory The access sequence when burst cycles are used can be divided into the following two types First access cycle The first access cycle is the start cycle for the burst access and operates in the same way as the normal single access cycle Page access cycle The page access cycle ...

Page 591: ... first cycle is repeated However if the data bus width is set to 32 bits the BST bits of the ACR register are 10B set the burst length to 4 or less A malfunction occurs if the burst length is set to 8 If burst access is enabled burst access is used when prefetch access or transfer with a larger size than the specified data bus width is performed For example if word access to an area whose data bus...

Page 592: ...01xxB in the ACR register enables the address data multiplex interface to be set If the address data multiplex interface is set set 8 bits or 16 bits for the data bus width DBW1 0 bits In the address data multiplex interface the total of 3 cycles of 2 address output cycles 1 data cycle becomes the basic number of access cycles In the address output cycles AS is asserted as the output address latch...

Page 593: ...Address Data Multiplex Interface with External Wait shows the operation timing chart for TYP3 0 0101B AWR 1008H Figure 7 2 Timing Chart for the Address Data Multiplex Interface with External Wait Making a setting such as TYP3 0 01x1B in the ACR register enables RDY input in the address data multiplex interface CSn RD WRn Setup Figure 7 3 Timing Chart for the Address Data Multiplex Interface CSn RD...

Page 594: ...dress output cycle to be extended by one cycle as shown in Figure 7 3 Timing Chart for the Address Data Multiplex Interface CSn RD WRn Setup allowing the address to be latched directly to the rising edge of AS Use this setting if you want to use AS as an ALE Address Latch Enable strobe without using MCLK address 31 0 address 15 0 address 15 0 data 15 0 data 15 0 MCLK AS CSn RD A 31 0 D 31 16 D 31 ...

Page 595: ...ontinue as long as the prefetch buffer clear conditions are not met For an access that mixes multiple prefetch enabled areas and multiple prefetch disabled areas the prefetch buffer always holds data of the prefetch enabled area accessed last Since in this case access to prefetch disabled areas does not affect the prefetch buffer state at all data in the prefetch buffer is not wasted even if prefe...

Page 596: ...refetch buffer is infrequent and the external bus tends to be idle For example if the bus width is set to 16 bits and the burst length is set to 8 the amount of data read into the buffer in one prefetch operation is 16 bytes Thus a new prefetch access can be started only after the prefetch buffer is completely empty Adjust the optimum burst length to suit use and the environment after taking the a...

Page 597: ...e the external bus is accessed again Data read in this case is not stored in the buffer Also no prefetch access is performed If a buffer write hit occurs A buffer write hit is as follows When the address of just one byte that matches is found in the buffer in an access to write to a prefetch enabled area In this case the external bus is accessed again but no prefetch access is performed before a n...

Page 598: ...gure 4 9 1 shows the operation timings assuming that page hits and CAS latency 2 are set Figure 9 1 Burst Read Write Timing Chart All of the A13 to A0 pins may not be used depending on the SDRAM capacity See Section Memory Connection Examples The MCLK is a clock signal input to SDRAM Signals such as addresses data and commands are input to SDRAM at the rise of the MCLK Set the W05 and W04 bits in ...

Page 599: ...s performed after the PRE charge and ACTV commands are issued Set the W01 and W00 bits in the area wait register AWR to the RAS precharge cycle tRP according to the SDRAM FCRAM standards Set the W14 to W12 bits in the area wait register AWR to the RAS to CAS delay tRCD according to the SDRAM FCRAM standards Single Read Write Operation Timing Figure 9 4 shows the operation timings assuming that CAS...

Page 600: ...the PRE command Auto refresh Operation Timing Figure 9 5 shows auto refresh operation timings Figure 9 5 Auto refresh Timing Chart The refresh command is issued every refresh control register s RCR s RFINT5 RFINT0 value x 32 cycles and access is restarted upon completion of each refresh Set the TRC bit in the refresh control register RCR according to the SDRAM FCRAM standards Satisfy the maximum R...

Page 601: ...e 1 Set SELF bit to 1 2 Issue the REF command the number of times set in the RFC2 to RFC0 bits 3 Issue SELF command Self refresh mode reset procedure 1 Set the SELF bit to 0 or access to SDRAM FCRAM 2 Issue SELFX command 3 Issue the REF command the number of times set in the RFC2 to RFC0 bits 4 Transition to the normal access state 9 2 Power on Sequence This section describes the power on sequence...

Page 602: ...e 9 4 Address Multiplexing Format This section describes the address multiplexing format Address Multiplexing Format SDRAM FCRAM access addresses correspond to row bank and column addresses differently depending on the settings of the ASZ3 to ASZ0 DBW1 and DBW0 PSZ2 to PSZ0 and BANK bits Addresses are arranged in the order of Column BANK and Row addresses starting from the least significant bit Se...

Page 603: ... CAS BA COLUMN 0 7 8 9 31 21 22 ROW BA COLUMN 0 1110 9 31 23 24 ROW 1 12 BA COLUMN 0 1110 13 31 25 26 ROW 1 12 2 A8 A9 A10 A11 A12 A14 A15 A7 A6 A5 A4 A3 A2 A1 A0 Access address bit Access address bit Access address bit A8 A9 A10 A11 A14 A15 A7 A6 A5 A4 A3 A2 A1 A0 A8 A9 A10 A11 A12 A14 External address pin External address pin External address pin A7 A6 A5 A4 A3 A2 A1 A0 4M bytes set ASZ to 0110B...

Page 604: ... on the bus width A10 AP A10 AP A10 for row address output otherwise AP A11 to A13 A11 to A13 Connected to the address used for SDRAM FCRAM A14 BA0 BA for 2 bank product A15 BA1 The pin is not used for a two bank module D31 to D0 DQ The connection changes depending on the endian method and data bus width For detailed connection see Section 4 Endian and Bus Access DQMUU DQMUL DQMLU DQMLL DQM The co...

Page 605: ...four SDRAM modules Total data width of 16 bits Use one or two SDRAM modules Figure 9 8 shows how to use 64 Mbit SDRAM two bank addresses and 12 row addresses A11 A0 This LSI CS6 or CS7 SCAS SRAS SWE MCLKE DQMUU MCLKO DQ31 0 SDRAM No 1 CS CAS RAS WE CKE DQM CLK DQ7 DQ0 IA11 IA0 SDRAM No 2 CS CAS RAS WE CKE DQM CLK DQ7 DQ0 IA11 IA0 SDRAM No 3 CS CAS RAS WE CKE DQM CLK DQ7 DQ0 IA11 IA0 SDRAM No 4 CS ...

Page 606: ...9 9 shows 64 Mbit SDRAM one bank address and 12 row addresses Figure 9 9 Using 64 Mbit A11 A0 This LSI CS7 CS6 SCAS SRAS SWE MCLKE DQMUU MCLKO DQ31 0 IA11 IA0 SDRAM No 1 CS CAS RAS WE CKE DQML CLK DQ15 DQ0 BA1 SDRAM No 2 CS CAS RAS WE CKE DQML CLK DQ15 DQ0 SDRAM No 3 CS CAS RAS WE CKE DQML CLK DQ15 DQ0 IA11 IA0 SDRAM No 4 CS CAS RAS WE CKE DQML CLK DQ15 DQ0 15 0 31 16 15 0 31 16 DQMU DQMU DQMU DQM...

Page 607: ...591 Chapter 31 External Bus 9 SDRAM FCRAM Interface Operation SDRAM No 2 is not required when the device is used with only one SDRAM module ...

Page 608: ...cycle transfer internal RAM I O RAM 2 cycle transfer external I O 2 cycle transfer I O external 10 1 DMA Fly By Transfer I O Memory This section explains DMA fly by transfer I O memory DMA Fly By Transfer I O Memory Figure 10 1 Timing Chart for DMA Fly By Transfer I O Memory shows the operation timing chart for TYP3 0 0000B AWR 0008H IOWR 41H Figure 10 1 Timing Chart for DMA Fly By Transfer I O Me...

Page 609: ...rea without negating the chip select neither CSn RD WRn setup delay nor RD WRn CSn hold delay is inserted If a setup cycle for determining the address or a hold cycle for determining the address is needed set 1 for the address CSn delay setting W02 bit of the AWR register For I O on the data output side a read strobe of three bus cycles extended by the I O wait cycle and I O hold wait cycle is gen...

Page 610: ... the HLD bit of the IOWR0 3 registers extends the I O read cycle by one cycle Setting bits WR1 0 bits of the IOWR0 3 registers enables 0 3 write recovery cycles to be inserted If the write recovery cycle is set to 1 or more a write recovery cycle is always inserted after write access Setting bits IW3 0 of the IOWR0 3 registers enables 0 15 wait cycles to be inserted If wait is also set on the memo...

Page 611: ...tended by the I O wait cycle is generated The I O hold wait cycle does not affect the write strobe However the address and CS signal are retained until the fly by bus access cycles end 10 3 DMA Fly By Transfer I O SDRAM FCRAM This section describes the operation of DMA fly by transfer I O device to SDRAM FCRAM DMA Fly By Transfer I O SDRAM FCRAM Figure 4 10 3 shows an operation timing chart assumi...

Page 612: ...eration Figure 10 3 Timing Chart for DMA Fly by Transfer I O to SDRAM FCRAM memory address DACKn IORD DEOPn DACKn DEOPn DREQn FR30 compatible mode Basic mode MCLK AS CSn SCAS A31 to 0 D31 to 0 WRn SWE SRAS Basic cycle I O wait cycle I O hold wait ...

Page 613: ...t cycle does not affect the write strobe Note however that the CS signal is retained until the fly by bus access cycles end For fly by transfer from an I O device to SDRAM FCRAM be sure to set the HLD bit in the DMAC I O wait register IOWR to 1 to enable the I O hold wait cycle Fly by transfer must always be performed between data buses having the same bus width 10 4 DMA Fly By Transfer SDRAM FCRA...

Page 614: ...hortest Figure 10 4 Timing Chart for DMA Fly by Transfer SDRAM FCRAM to I O with Page Hits Shortest column address IOWR DACKn DEOPn DREQn Basic mode MCLK CSn SCAS A31 to 0 D31 to 0 WRn SWE SRAS basic cycle I O wait cycle I O hold wait MCLKE I O basic cycle SDRAM Data setup ...

Page 615: ... O access so that the I O access is extended to be longer than the SDRAM access When the I O device requires data setup therefore the I O wait cycle must be set such that I O access is longer than the maximum SDRAM access cycle For the above settings set the number of I O wait cycles to at least 4 For SDRAM FCRAM on the data output side a READ command is issued at the timing that satisfies the I O...

Page 616: ...oblem prepare an external circuit as illustrated in Figure 4 10 6c to use an external wait cycle based on the CAS signal thereby extending I O access to reserve data setup time Figure 10 6 Sample Circuit Solving a Fly by Penalty Using External Wait Cycles Based on the CAS Signal CL 2 Note For CL 3 provide two stages of MCLK based FF to cause a delay of another cycle If any device requires an exter...

Page 617: ...DRAM data output to the I O device can be reserved for one cycle regardless of a page hit or miss in SDRAM Set the external wait using the RYE0 and RYE1 bits in the DMAC I O wait register such that the RDY function of the DMA fly by access channel to be used is enabled When the CAS latency is 3 SDRAM data output is delayed one cycle Add one stage of FF by the MCLK to input the signal delayed one c...

Page 618: ...for TYP3 0 0000B AWR 0008H IOWR 00H Figure 10 8 Timing Chart for 2 cycle Transfer Internal RAM External I O RAM shows a case in which a wait is not set on the I O side Figure 10 8 Timing Chart for 2 cycle Transfer Internal RAM External I O RAM The bus is accessed in the same way as an interface when DMAC transfer is not performed DACKn DEOPn is not output in the internal RAM access cycles 10 6 2 C...

Page 619: ...et for memory and I O Figure 10 9 Timing Chart for 2 Cycle Transfer External I O The bus is accessed in the same way as an interface when the DMAC transfer is not performed In basic mode DACKn DEOPn is output in both transfer source bus access and transfer destination bus access 10 7 2 Cycle Transfer I O External This section explains 2 cycle transfer I O external operation memory address I O addr...

Page 620: ...and I O Figure 10 10 Timing Chart for 2 Cycle Transfer I O External The bus is accessed in the same way as an interface when the DMAC transfer is not performed In basic mode DACKn DEOPn is output both in the transfer source bus access and transfer destination bus access 10 8 2 Cycle Transfer I O SDRAM FCRAM This section describes the operation of two cycle transfer I O device to SDRAM FCRAM memory...

Page 621: ...t for Two cycle Transfer I O to SDRAM FCRAM 10 9 2 Cycle Transfer SDRAM FCRAM I O This section describes the operation of two cycle transfer SDRAM FCRAM to I O device 2 Cycle Transfer SDRAM FCRAM I O Figure 1 10 12 shows a timing chart for two cycle transfer SDRAM FCRAM to I O MC LK A31 to 0 AS CS n memory address I O address idle WRn SWE RD D31 to 0 CS n DACKn DEOPn DACKn DEOPn DREQn FR30 compati...

Page 622: ...DMA Access Operation Figure 10 12 Timing Chart for Two cycle Transfer SDRAM FCRAM to I O MCLK A31 to 0 AS CSn RD CSn memory address I O address WRn SWE D31 to 0 DACKn DEOPn DACKn DEOPn DREQn FR30 compatible mode Basic mode SRAS SCAS ...

Page 623: ... External Bus 10 DMA Access Operation Bus access is the same as that of the interface for non DMA transfer In base mode DACKn DEOPn is output at both of transfer source bus access and transfer destination bus access ...

Page 624: ...us right Releasing the Bus Right Figure 11 1 Timing Chart for Releasing the Bus Right shows the timing chart for releasing the bus right Figure 11 2 Timing Chart for Releasing the Bus Right shows the timing chart for acquiring the bus right Figure 11 1 Timing Chart for Releasing the Bus Right MCLK A23 to A0 AS CSn D31 to D16 Read BRQ BGRNT 1 cycle RD ...

Page 625: ... set to high impedance and then BGRNT is asserted one cycle later When the bus right is acquired BGRNT is negated and then each pin is activated one cycle later CSn is set to high impedance only if the SREN bit in the ACR0 7 registers is set If all areas enabled by the CSER register are shared the SREN bit of the ACR register is 1 AS BAA RD WE and WR0 WR3 are set to high impedance MCLK A23 to A0 A...

Page 626: ...e CHER bit corresponding to the applicable area Set the CSER bit corresponding to the applicable area 3 The CS0 area is enabled after a reset is released If the area is used as a program area the register contents need to be rewritten while the CSER bit is 1 In this case make the settings described in 2 to 4 above in the initial state with a low speed internal clock Then switch the clock to a high...

Page 627: ...are mixed be sure to make the following setting in all areas that will be used Set at least one read write idle cycle other than AWR W07 W06 00B Set at least one write recovery cycle other than AWR W05 W04 00B However if WR0 WR3 are disabled ROM only is connected in the area TYP3 0 0x0xB where WR0 WR3 are used as a write strobe the above restriction does not apply Also the above restriction does n...

Page 628: ...612 Chapter 31 External Bus 13 Notes on Using the External Bus Interface ...

Page 629: ... serial data communication interface for transmitting serial data to and receiving data from another CPU or peripheral devices It has the functions listed in table 1 1 Table 1 1 USART functions Item Function Data buffer Full duplex Serial Input 5 times oversampling in asynchronous mode Transfer mode Clock synchronous start stop synchronization and start stop bit option Clock asynchronous using sta...

Page 630: ...ication function multiprocessor mode One to n communication one master to n slaves This function is supported both for master and slave system Synchronous mode Function as Master or Slave USART Transceiving pins Direct access possible LIN bus options Operation as master device Operation as slave device Generation of LIN Sync break Detection of LIN Sync break Detection of start stop edges in LIN Sy...

Page 631: ...ous multiprocessor mode 1 0 2 Synchronous normal mode 1 1 3 Asynchronous LIN mode Table 1 4 USART interrupts Interrupt cause Interrupt number Interrupt control register Interrupt Vector Register name Address Offset Default address USART04 reception interrupt 66 42H ICR25 0459H 2F4H 000FFEF4H USART04 transmission interrupt 67 43H ICR25 0459H 2F0H 000FFEF0H ...

Page 632: ...l Circuit Transmission Shift Register Transmission Data Register Error Detection Circuit Oversampling Unit Interrupt Generation Circuit LIN Break Generation LIN Break and Synch Field Detection Bus Idle Detection Circuit Serial Mode Register SMR04 Serial Control Register SCR04 Serial Status Register SSR04 Extended Com Contr Reg ECCR04 Extended Status Contr Reg ESCR04 FIFO Control Register FCR04 FIF...

Page 633: ... the parity of the reception data Reception Shift Register The reception shift register fetches reception data input from the SIN04 pin shifting the data bit by bit When reception is complete the reception shift register transfers receive data to the RDR04 register RDR FIFO TDR FIFO Reception shift register Transmission shift register Received Parity counter Received Bit counter Start bit Detectio...

Page 634: ...the SIN04 pin for five times It is switched off in synchronous operation mode Interrupt Generation Circuit The interrupt generation circuit administers all cases of generating a reception or transmission interrupt If a corresponding enable flag is set and an interrupt case occurs the interrupt will be generated immediately LIN Break and Synchronization Field Detection Circuit The LIN break and LIN...

Page 635: ...tus Control Register This register provides several LIN functions direct access to the SIN04 and SOT04 pin and setting for the USART synchronous clock mode Extended Communication Control Register The extended communication control register provides bus idle recognition interrupt settings synchronous clock settings and the LIN break generation FIFO Control Register With the FCR4 register the TX RX ...

Page 636: ...ired to use pin SIN04 Port I O or serial data input CMOS output and CMOS hystere sis CMOS Auto motive hysteresis TTL input Program mable Provided Set port function mode PFR bit0 1 EPFR bit0 0 SOT04 Port I O or serial data output Set to output enable mode SMR04 SOE 1 Set port function mode PFR bit1 1 EPFR bit1 0 SCK04 Port I O or serial clock input output Set port function mode PFR bit2 1 EPFR bit2...

Page 637: ...lengths selects a frame data format in mode 1 clears the reception error flag and specifies whether to enable transmission and reception Table 4 1 USART04 Registers Address bit 15 bit 8 bit 7 bit 0 060H 061H SCR04 Serial Control Register SMR04 Serial Mode Register 062H 063H SSR04 Serial Status Register RDR04 TDR04 Rx Tx Data Register 064H 065H ESCR04 Extended Status Control Reg ECCR04 Extended Com...

Page 638: ...le Reception 1 Enable Reception bit10 CRE Clear Reception errors write read 0 ignored read always returns 0 1 Clear all reception errors PE FRE ORE bit11 AD Address Data bit 0 Data bit 1 Address bit bit12 CL Character Data frame Length 0 7 bits 1 8 bits bit13 SBL Stop bit length 0 1 stop bit 1 2 stop bits bit14 P Parity setting 0 Even Parity enabled 1 Odd Parity enabled bit15 PEN Parity Enable 0 P...

Page 639: ...s bit specifies the data format in multiprocessor mode 1 Writing to this bit determines an address or data frame to be sent next reading from it returns the last received kind of frame 1 indicates an address frame 0 indicates a usual data frame Note During a RMW Read cycle the AD bit returns the value to be sent instead of the last received AD bit see table below bit10 CRE Clear reception error fl...

Page 640: ...erial Clock Input 1 Internal Serial Clock Output bit2 UPCL USART programmable clear Software Reset write read 0 ignored always 0 1 Reset USART bit3 REST Restart dedicated Reload Counter write read 0 ignored always 0 1 Restart Counter bit4 EXT External Serial Clock Source enable 0 Use internal Baud Rate Generator Reload Counter 1 Use external Serial Clock Source bit5 OTO One to one external clock I...

Page 641: ...iting 0 to it has no effect Reading from this bit always returns 0 bit2 UPCL USART programmable clear bit Software reset Writing a 1 to this bit resets USART immediately The register settings are preserved Possible reception or transmission will cut off All error flags are cleared and the Reception Data Register RDR04 contains 00h Writing 0 to this bit has no effect Reading from it always returns ...

Page 642: ...e LSB first 1 send receive MSB first bit11 TDRE Transmission data register empty 0 Transmission data register is full 1 Transmission data register is empty bit12 RDRF Reception data register full 0 Reception data register is empty 1 Reception data register is full bit13 FRE Framing error 0 No framing error occurred 1 A framing error occurred during reception bit14 ORE Overrun error 0 No overrun er...

Page 643: ...egister RDR04 This bit is set to 1 when reception data is loaded into RDR04 and can only be cleared to 0 when the reception data register RDR04 is read A reception interrupt request is output when this bit and the RIE bit are 1 bit11 TDRE Transmission data empty flag bit This flag indicates the status of the transmission data register TDR04 This bit is cleared to 0 when transmission data is writte...

Page 644: ...is cleared automatically to 0 when RDR04 is read Also the reception interrupt is cleared if it is enabled and no error has occurred Data in RDR04 is invalid when a reception error occurs SSR04 PE ORE or FRE 1 Transmission When data to be transmitted is written to the transmission data register in transmission enable state it is transferred to the transmission shift register then converted to seria...

Page 645: ...alling clock edge inverted clock bit9 CCO Continuous Clock Output Mode 2 0 Continuous Clock Output disabled 1 Continuous Clock Output enabled bit10 SIOP Serial Input Output Pin Access write if SOPE 1 read 0 SOT04 is forced to 0 reading the actual value of SIN04 1 SOT04 is forced to 1 bit11 SOPE Enable Serial Output pin direct Access 0 Serial Output pin direct access disable 1 Serial Output pin dir...

Page 646: ...ct access enable Setting this bit to 1 enables the direct write to the SOT04 pin if SOE 1 SMR04 bit10 SIOP Serial Input Output Pin direct access Normal read instructions always return the actual value of the SIN04 pin Writing to it sets the bit value to the SOT04 pin if SOPE 1 During a Read Modify Write instruction the bit returns the SOT04 value in the read cycle bit9 CCO Continuos Clock Output e...

Page 647: ...s start stop bits in mode 2 0 No start stop bits in synchronous mode 2 1 Enable start stop bits in synchronous mode 2 bit4 SCDE Serial Clock Delay enable in mode 2 0 disable clock delay 1 enable clock delay bit5 MS Master Slave function in mode 2 0 Master mode generating serial clock 1 Slave mode receiving external serial clock bit6 LBR Set LIN break write read 0 ignored always read 0 1 Generate L...

Page 648: ...ynchronous mode 2 If master is selected USART generates the synchronous clock by itself If slave mode is selected USART receives external serial clock Caution If slave mode is selected the clock source must be external and set to One to One SMR04 SCKE 0 EXT 1 OTO 1 bit4 SCDE Serial clock delay enable bit If this bit is set the serial output clock is delayed by 1 CLKP cycle or half of its period in...

Page 649: ... or word access 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 B R W R W R W R W R W R W R W bit 0 7 BGR0 Baud rate Generator Register 1 write Write bit 0 7 of reload value to counter read Read bit 0 7 of actual count bit 8 15 BGR1 Baud rate Generator Register 0 write Write bit 8 15 of reload value to counter read Read bit 8 15 of actual count R W Readable and writable R W R W...

Page 650: ...O 1 Select reading status from TX FIFO bit 1 ETX control TX FIFO on off 0 Disables TX FIFO 1 Enables TX FIFO bit 2 ERX control RX FIFO on off 0 Disables RX FIFO 1 Enables RX FIFO bit 3 not used always read 0 bit 4 RXL0 RX Triggerlevel 0 RX Triggerlevel Bit 0 bit 5 RXL1 RX Triggerlevel 0 RX Triggerlevel Bit 1 bit 6 RXL2 RX Triggerlevel 0 RX Triggerlevel Bit 2 bit 7 RXL3 RX Triggerleve 0 RX Triggerl...

Page 651: ...d If this bit is set to 0 the fifo status register shows the number of valid data from the RX fifo If this bit is set to 1 the fifo status register shows the number of valid data from the TX fifo bit 1 ETX enable TX fifo If this bit is set to 0 the TX fifo is disabled fifo data is cleared If this bit is set to 1 the TX fifo is enabled bit 2 ERX enable RX fifo If this bit is set to 0 the RX fifo is...

Page 652: ...0 0 0 0 0 0 0 0 B R R R R R R R R bit 0 FIFO valid data number 0 FIFO number of valid Data Bit 0 bit 1 FIFO valid data number 0 FIFO number of valid Data Bit 1 bit 2 FIFO valid data number 0 FIFO number of valid Data Bit 2 bit 3 FIFO valid data number 0 FIFO number of valid Data Bit 3 bit 4 FIFO valid data number 0 FIFO number of valid Data Bit 4 bit 5 not used always read 0 bit 6 not used always ...

Page 653: ...FO number of valid Data shows the number of valid FIFO Data for RX and TX Fifo depending on selection bit bit 2 FIFO number of valid Data shows the number of valid FIFO Data for RX and TX Fifo depending on selection bit bit 3 FIFO number of valid Data shows the number of valid FIFO Data for RX and TX Fifo depending on selection bit bit 4 FIFO number of valid Data shows the number of valid FIFO Dat...

Page 654: ... can be read RDRF if FIFO is enabled trigger level is reached Overrun error i e RDRF 1 and RDR04 was not read by the CPU ORE Table 5 1 Interrupt control bits and interrupt causes of USART Reception transmission ICU Interrupt request flag bit Flag Register Operation mode Interrupt cause Interrupt cause enable bit How to clear the Interrupt Request 0 1 2 3 Reception RDRF SSR04 x x x x receive data i...

Page 655: ... in this case after 9 bit times the reception error flags are set to 1 therefore the RIE flag has to be set to 0 or the RXE flag has to be set to 0 if only a LIN synch break detect is desired In the other case a reception error interrupt would be generated first and the interrupt handler routine has then to wait for LBD 1 The interrupt and the LBD flag are cleared after writing a 1 to the LBD flag...

Page 656: ...top bit is detected in mode 0 1 2 if SSM 1 3 or the last data bit was read in mode 2 if SSM 0 Note If a reception error has occurred the Reception Data Register RDR04 contains invalid data in each mode Figure 5 2 Reception operation and flag set timing Note The example in figure 5 2 does not show all possible reception options for mode 0 and 3 Here it is Transmission data Reception data Start bit ...

Page 657: ...The Transmission Data Register Empty TDRE flag bit of the SSR04 indicates an empty TDR04 Because the TDRE bit is read only it only can be cleared by writing data into TDR04 The following figure demonstrates the transmission operation and flag set timing for the four modes of USART Figure 5 4 Transmission operation and flag set timing Note The example in figure 5 4 does not show all possible transm...

Page 658: ...s designed as shown below One of the following three types of baud rates can be selected Baud Rates Determined Using the Dedicated Baud Rate Generator Reload Counter USART has two independent internal reload counters for transmission and reception serial clock The baud rate can be selected via the 15 bit reload value determined by the Baud Rate Generator Register 0 and 1 BGR0 1 The reload counter ...

Page 659: ...ud rate is 19200 baud then the reload value v is v 16 106 19200 1 832 The exact baud rate can then be recalculated bexact F v 1 here it is 16 106 833 19207 6831 Note Setting the reload value to 0 stops the reload counter Note The minimum recommended division ratio is 4 i e reload value is 3 due to RX oversampling filter in asynchronous communication modes mode 0 1 and 3 Internal data bus EXT REST ...

Page 660: ...0 08 153600 51 0 16 64 0 16 103 0 16 129 0 16 155 0 16 207 0 16 125000 63 0 79 0 127 0 159 0 191 0 255 0 115200 86 0 22 138 0 08 173 0 22 207 0 16 278 0 08 76800 103 0 16 129 0 16 207 0 16 259 0 16 311 0 16 416 0 08 57600 138 0 08 173 0 22 277 0 08 346 0 06 416 0 08 555 0 08 38400 207 0 16 259 0 16 416 0 08 520 0 03 624 0 832 0 04 28800 277 0 08 346 0 01 554 0 01 693 0 06 832 0 03 1110 0 01 19200 ...

Page 661: ...start SMR04 REST bit Reception Reload Counter Start bit falling edge detection in asynchronous mode Programmable Restart If the REST bit of the Serial Mode Register SMR04 is set by the user both Reload Counters are restarted at the next clock cycle This feature is intended to use the Transmission Reload Counter as a small timer The following figure illustrates a possible usage of this feature assu...

Page 662: ...te If USART is reset by setting SMR04 UPCL the Reload Counters will restart too Automatic Restart In asynchronous UART mode if a falling edge of a start bit is detected the Reception Reload Counter is restarted This is intended to synchronize the serial input shifter to the incoming serial data stream MCU REST Reload Value 37 36 35 100 99 98 97 96 95 94 93 92 91 90 89 88 87 Read BGR0 1 Data Bus 90...

Page 663: ...e synchronization method must be common to all CPUs Select an operation mode as follows In the one to one connection method operation mode 0 or 2 must be used in the two CPUs Select operation mode 0 for asynchronous transfer mode and operation mode 2 for synchronous transfer mode Note that one CPU has to set to the master and one to the slave in synchronous mode 2 Select operation mode 1 for the m...

Page 664: ...ty bit 1 or 2 stop bits can be selected The calculation formula for the bit length of a transfer frame is Length 1 d p s d number of data bits 7 or 8 p parity 0 or 1 s number of stop bits 1 or 2 Figure 7 1 Transfer data format operation modes 0 and 1 Note If BDS Bit of the Serial Status Register SSR04 is set to 1 MSB first the bit stream processes as D7 D6 D1 D0 P During Reception both stop bits a...

Page 665: ...econd stop bit In mode 0 parity overrun and framing errors can be detected In mode 1 overrun and framing errors can be detected Parity is not provided By setting the Parity Enable PEN bit of the Serial Control Register SCR04 the USART provides parity calculation during transmission and parity detection and check during reception in mode 0 and mode 2 if the SSM bit of ECCR04 is set Even parity is s...

Page 666: ...O extended serial the number of the transmission and reception bits has to be equal to the number of clock cycles Note that if start stop bits communication is enabled the number of clock cycles has to match with the quantity for the additional start and stop bit s If the internal clock dedicated reload counter is selected the data receiving synchronous clock is generated automatically if data is ...

Page 667: ...tes this Figure 7 5 Continuous clock output in mode 2 Data signal mode NRZ data format is selected if ECCR04 INV 0 otherwise the signal mode for the serial data input and output pin is RZ Error Detection If no Start Stop bits are selected ECCR04 SSM 0 only overrun errors are detected Communication For initialization of the synchronous mode the following settings have to be made Baud Rate Generator...

Page 668: ...ces have to synchronize to the master and the desired baud rate remains fixed in master operation after initialization Writing a 1 into the LBR bit of the Extended Status Communication Register ECCR04 generates a 13 16 bit times low level on the SOT04 pin which is the LIN synchronization break and the start of a LIN message Thereby the TDRE flag of the Serial Status Register SSR04 goes 0 and is re...

Page 669: ...n The fifth falling edge resets the ICU signal Therefore the ICU has to be configured for the LIN input capture PFR14 4 1 EPFR14 4 1 and its interrupts have to be enabled ICS4 The values of th ICU counter register after the first Interrupt a and after the second interrupt b yield the BGR value without timer overflow BGR value b a 8 with timer overflow BGR value max b a 8 where max is the timer max...

Page 670: ... own transmission and is used for error handling if something is physically wrong with the single wire LIN bus Note Write the desired value to the SIOP pin before enabling the output pin access to prevent undesired peaks The peaks can occur because SIOP holds the last written value During a Read Modify Write operation the SIOP bit returns the actual value of the SOT04 pin in the read cycle instead...

Page 671: ...irectional communication 7 6 Master Slave Communication Function Multiprocessor Mode USART communication with multiple CPUs connected in master slave mode is available for both master or slave systems bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCR04 SMR0 4 PEN P SBL CL AD CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE Mode 0 x 0 0 0 x 0 0 0 Mode 2 x x 0 1 0 0 0 SSR04 TDR04 RDR04 PE ORE FRE RDRF TDR...

Page 672: ...used for the master or slave CPU Figure 7 11 Connection example of USART master slave communication Function Selection Select the operation mode and data transfer mode for master slave communication as shown in table 7 3 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCR04 SMR0 4 PEN P SBL CL AD CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE Mode 1 x x 0 0 1 x 0 0 0 1 SSR04 TDR04 RDR04 PE ORE FRE RDRF ...

Page 673: ...ss data using a program When the address data indicates the address assigned to a slave CPU the slave CPU communicates with the master CPU ordinary data Figure 7 12 shows a flowchart of master slave communication multiprocessor mode Operation mode Data Parity Synchro nization method Stop bit Bit direction Master CPU Slave CPU Address transmis sion and reception Mode 1 send AD bit Mode 1 receive AD...

Page 674: ... RXE 1 Send Slave Address Set 0 in AD bit Communicate with slave CPU Is communication complete Communicate with another slave CPU Set TXE RXE 0 End NO YES NO YES Master CPU Start Set operation mode 1 Set SIN pin as the serial data input pin Set SOT pin as the serial data output pin Set 7 or 8 data bits Set 1 or 2 stop bits Slave CPU Set TXE RXE 1 Receive Byte Is AD bit 1 Does Slave Address match C...

Page 675: ... example of a small LIN Bus system 7 8 Sample Flowcharts for USART in LIN Communication Operation Mode 3 This section contains sample flowcharts for USART in LIN communication bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCR04 SMR04 PEN P SBL CL AD CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE Mode 3 x x x 0 1 1 x 0 0 0 1 SSR04 TDR04 RDR04 PE ORE FRE RDRF TDRE BDS RIE TIE Set transmission data durin...

Page 676: ...end Synch Break Send Sleep Mode Y N Send Identify Field TDR Id Write to slave Y N TIE 0 RIE 1 Read data from slave RIE 0 Write data to slave TIE 0 TIE 1 Errors occurred Y N Error Handler Send Sleep Mode TDR 0x80 Wake up from CPU Y N RIE 1 TIE 0 0x00 0x80 or 0xC0 N Y RIE 0 Send Wake up signal RIE 0 TIE 1 TDR 0x80 received write 1 to ECCR LBR TIE 1 TDRE 1 Transm Interrupt Send Synch Field TDR 0x55 ...

Page 677: ... to send data Receive data checksum RIE 0 TIE 1 Calculate checksum Send data TIE 0 C Errors occurred Y N C Error handler C E continued next page S on next page slave action from LIN master Write 0 to LBD waiting slave action to clear interrupt waiting slave action ICU E Enable ICU inter rupt both edges ICU Interrupt Read ICU value and store it Clear Interrupt Read ICU value Calculate new baud rate...

Page 678: ...T LIN FIFO 7 USART Operation Figure 7 17 USART LIN slave flow chart part 2 S C Wake up from CPU Y N RIE 1 0x00 0x80 or 0xC0 N Y Send Wake up signal RIE 0 TIE 1 TDR 0x80 RIE 0 TIE 0 continuation from previous page received ...

Page 679: ...transmission interrupt request is enabled SSR04 TIE 1 Be sure to set the TIE flag to 1 after setting the transmission data to avoid an immediate interrupt Using LIN operation mode 3 The LIN features are also available in mode 0 transmitting receiving break but using mode 3 sets the USART data format automatically to LIN format 8N1 LSB first So break features are appliable for bus protocols other t...

Page 680: ...to the ICUs is controlled by the Port 14 function register PFR and EPFR If the PFR bit equals 1 and the EPFR bits equals 0 the ICU is connected to its corresponding input pin IN If the PFR bit equals 1 and the EPFR bits equals 1 the USARTs are connected to the ICU The user has to take into account that ICU4 and ICU5 share one free running timer prescaler LIN UART4 LSYN ICU4 IN ICU5 IN FREE RUN TIM...

Page 681: ...lave address Acknowledging upon slave address reception can be disabled Master only operation Address masking to give interface several slave addresses in 7 and 10 bit mode Up to 400 kBit transfer rate Possibility to use built in noise filters for SDA and SCL Can receive data at 400 kBit if R Bus Clock is higher than 6 MHz regardless of prescaler setting Can generate MCU interrupts on transmission...

Page 682: ...ation Loss Detector BER IBCR BEIE INTE INT SCC IBCR MSS ACK GCAA Interrupt Request Start Stop Condition Generator IDAR Slave Address Comparator AAS IBSR Slave SCL Clock Divider 2 by 12 SCL Duty Cycle Generator Clock Selector ITBA ITMK Shift Clock Generator 2 3 4 5 32 ACK Generator Bus Observer ITMK ENSB enable 10 bit mode R Bus Clock CLKP MCU IRQ ISBA ISMK ISMK enable 7 bit mode ENTB received ad l...

Page 683: ... Default value 0 0 0 0 0 0 0 0 Address 0000D1H 7 6 5 4 3 2 1 0 IBSR0 Bus status register TA9 TA8 Bit no Read write R W R W Default value 0 0 0 0 0 0 0 0 Ten Bit Address high byte Address 0000D2H 15 14 13 12 11 10 9 8 ITBAH0 TA7 TA6 TA5 TA4 TA3 TA2 TA1 TA0 Bit no Read write R W R W R W R W R W R W R W R W Default value 0 0 0 0 0 0 0 0 Address 0000D3H 7 6 5 4 3 2 1 0 ITBAL0 Ten Bit Address low byte ...

Page 684: ...dress 0000D6H 15 14 13 12 11 10 9 8 ISMK0 SA6 SA5 SA4 SA3 SA2 SA1 SA0 Bit no Read write R W R W R W R W R W R W R W Default value 0 0 0 0 0 0 0 0 Address 0000D7H 7 6 5 4 3 2 1 0 ISBA0 Seven Bit Address register D7 D6 D5 D4 D3 D2 D1 D0 Bit no Read write R W R W R W R W R W R W R W R W Default value 0 0 0 0 0 0 0 0 Address 0000D9H 7 6 5 4 3 2 1 0 IDAR0 Data register NSF EN CS4 CS3 CS2 CS1 CS0 Bit no...

Page 685: ...his bit is set the EN bit in the ICCR0 register is cleared the I2 C interface goes to pause status data transfer is interrupted and all bits in the IBSR0 and the IBCR0 registers except BER BEIE and INT are cleared The BER bit must be cleared before the interface may be reenabled This bit is set to 1 if start or stop conditions are detected at wrong places during an address data transfer or during ...

Page 686: ...to it while the bus is idle MSS 0 and BB 0 a start condition is generated and the contents of the IDAR0 register which should be address data is sent If a 1 is written to the MSS bit while the bus is in use BB 1 and TRX 0 in IBSR2 MSS 0 in IBCR0 the interface waits until the bus is free and then starts sending If the interface is addressed as slave with write access data reception in the meantime ...

Page 687: ...e This bit enables the MCU interrupt generation It can only be changed by the user Setting this bit to 1 enables MCU interrupt generation when the INT bit is set to 1 by the hardware bit 8 INT INTerrupt This bit is the transfer end interrupt request flag It is changed by the hardware and can be cleared by the user It always reads 1 in a Read Modify Write access Write access Read access 0 The inter...

Page 688: ...start condition or to generate a stop condition In these cases the order of priority is as follows Next byte transfer and stop condition generation When 0 is written to the INT bit and 0 is written to the MSS bit the MSS bit takes priority and a stop condition is generated Next byte transfer and start condition generation When 0 is written to the INT bit and 1 is written to the SCC bit the SCC bit...

Page 689: ...bit 6 RSC Repeated Start Condition This bit indicates detection of a repeated start condition This bit is cleared at the end of an address data transfer ADT 0 or detection of a stop condition bit 5 AL Arbitration Loss This bit indicates an arbitration loss This bit is cleared by writing 0 to the INT bit or by writing 1 to the MSS bit in the IBCR0 register An arbitration loss occurs if the data sen...

Page 690: ...ending data as master It is set to 0 if the bus is idle BB 0 in IBCR0 an arbitration loss occured a 1 is written to the SCC bit during master interrupt MSS 1 and INT 1 the MSS bit is cleared during master interrupt MSS 1 and INT 1 the interface is in slave mode and the last transferred byte was not acknowledged the interface is in slave mode and it is receiving data the interface is in master mode...

Page 691: ...te access is detected else it is cleared after the first byte After the first second byte means a 0 is written to the MSS bit during a master interrupt MSS 1 and INT 1 in IBCR0 a 1 is written to the SCC bit during a master interrupt MSS 1 and INT 1 in IBCR0 the INT bit is being cleared the beginning of every byte transfer if the interface is not involved in the current transfer as master or slave ...

Page 692: ...e signal is sent to the master device and the AAS bit is set Additionally the interface acknowledges upon the the reception of a ten bit header with read access2 after a repeated start conditon All bits of the slave address may be masked using the ITMK0 register The received ten bit slave address is written back to the ITBA0 register it is only valid while the AAS bit in the IBSR0 register is 1 1 ...

Page 693: ... 9 bit 0 TMK Ten bit slave address MasK TM9 TM0 This register is used to mask the ten bit slave address of the interface Write access to these bits is only possible if the interface is disabled EN 0 in ICCR0 This can be used to make the interface acknowledge on multiple ten bit slave addresses Only the bits set to 1 in this register are used in the ten bit slave address comparision The received sl...

Page 694: ...2C Interface Registers IBSR0 register is 1 Note If the address mask is changed after the interface had been enabled the slave address should also be set again since it could have been overwritten by a previously received slave address ...

Page 695: ...abled ENSB 1 in the ISMK0 register If a match is detected an acknowledge signal is sent to the master device and the AAS bit is set All bits of the slave address may be masked using the ISMK0 register The received seven bit slave address is written back to the ISBA0 register it is only valid while the AAS bit in the IBSR0 register is 1 The interface does not compare the contents of this register t...

Page 696: ...t slave addresses Only the bits set to 1 in this register are used in the seven bit slave address comparision The received slave address is written back to the ISBA0 register and thus may be determined by reading the ISBA0 register if the AAS bit in the IBSR0 register is 1 Note If the address mask is changed after the interface had been enabled the slave address should also be set again since it c...

Page 697: ...BB 1 write data can be loaded to the register for serial transfer The data byte is loaded into the internal transfer register if the INT bit in the IBCR0 register is being cleared or the bus is idle BB 0 in IBSR0 In a read access the internal register is read directly therefore received data values in this register are only valid if INT 1 in the IBCR2 register D7 D6 D5 D4 D3 D2 D1 D0 Bit no Read w...

Page 698: ... be set by the user but may be cleared by the user and the hardware When this bit is set to 0 all bits in the IBSR0 register and IBCR0 register except the BER and BEIE bits are cleared the module is disabled and the I2 C lines are left open It is cleared by the hardware if a bus error occurs BER 1 in IBCR0 Warning The interface immediately stops transmitting or receiving if is it is being disabled...

Page 699: ... been determined by examining the last 8 cycles of a transfer This was done because the first cycle of all address or data transfers is longer than the other cycles To be more precise In case of an address transfer this first cycle is 3 prescaler periods longer than the other cycles in case of a data transfer it is 4 prescaler periods longer see figure below Table 2 1 I2C Prescaler Settings n CS4 ...

Page 700: ... sending of address and data bits The timings given in the figure are prescaler periods e g 9 means 9 times the prescaler count based on the R Bus clock The timings in the figure are only valid if no other device on the I2C bus influences the SCL timing Address sending Data sending 9 9 6 7 5 7 5 7 Time unit Prescaler cycles 5 7 5 7 ...

Page 701: ...es to generate a stop condition which might fail if another master pulls the SCL line low before the stop condition has been generated This will generate an interrupt after the next byte has been transferred Slave Address Detection In slave mode after a start condition is generated the BB is set to 1 and data sent from the master device is received into the IDAR0 register After the reception of ei...

Page 702: ...art condition SCC bit in IBCR0 followed by a ten bit address header with read access 1 1 1 1 0 A9 A8 1 Summary of the address data bytes 7 bit slave write access Start condition A6 A5 A4 A3 A2 A1 A0 0 7 bit slave read access Start condition A6 A5 A4 A3 A2 A1 A0 1 10 bit slave write access Start condition 1 1 1 1 0 A9 A8 0 A7 A6 A5 A4 A3 A2 A1 A0 10 bit slave read access Start condition 1 1 1 1 0 A...

Page 703: ...T 1 ACK LRB 0 AL 1 Enable Interface EN 1 Clear BER bit if set N N BER 1 Y N Ready to send data Start INT 1 ACK LRB 0 AL 1 Address slave for write Last byte transferred N N Y BER 1 Y IDAR0 Data Byte INT 0 N N N Y Y Y Y Y Bus error N stop condition repeated start or Generate Generate repeated start or stop condition Transfer End Slave did not ACK Restart transfer Check if AAS Restart transfer Check ...

Page 704: ...arts Example Of Receiving Data Start INT 1 Last byte transferred N Y BER 1 Y N Y Bus error N Address slave for read Clear ACK bit in IBCR0 if it s the last byte to read from slave INT 0 stop condition repeated start or Generate Transfer End reenable IF ...

Page 705: ... ADT 1 N Y Transfer failed remember to retry TRX 1 N Y Read received byte from IDAR0 register Change ACK bit if necessary Put next byte to be sent in IDAR0 register or clear MSS Clear INT bit New data transfer starts at next INT Change ACK bit if necessary TRX 1 N Y Put next byte to be sent in IDAR0 register Read received byte from IDAR0 register Change ACK bit if necessary End ISR GCA 1 N Y Gener...

Page 706: ...690 Chapter 33 I2C Controller 4 Programming Flow Charts ...

Page 707: ...rt A and B Bit rates up to 1 MBit s 32 up to 128 Message Objects Each Message Object has its own identifier mask Programmable FIFO mode concatenation of Message Objects Maskable interrupt Disabled Automatic Retransmission mode for Time Triggered CAN applications Programmable loop back mode for self test operation This chapter uses the following terms and abbreviations Term Meaning CAN Controller A...

Page 708: ...Base address of CAN1 0x00C100 Base address of CAN2 0x00C200 Base address of CAN3 0x00C300 Base address of CAN4 0x00C400 Base address of CAN5 0x00C500 Address Register Note 0 1 2 3 Base addr 0x00 Control Register Status Register bit 15 8 bit 7 0 bit 15 8 bit 7 0 reserved see descr CTRLR reserved see descr STATR Reset 0x00 Reset 0x01 Reset 0x00 Reset 0x00 Base addr 0x04 Error Counter Bit Timing Regi...

Page 709: ...it 15 8 bit 7 0 see descr IF1MCTR see descr IF1MCTR reserved reserved Reset 0x00 Reset 0x00 Reset 0x00 Reset 0x00 Base addr 0x20 IF1 Data A1 IF1 Data A2 Big Endian byte ordering bit 7 0 bit 15 8 bit 7 0 bit 15 8 Data 0 Data 1 Data 2 Data 3 Reset 0x00 Reset 0x00 Reset 0x00 Reset 0x00 Base addr 0x24 IF1 Data B1 IF1 Data B2 Big Endian byte ordering bit 7 0 bit 15 8 bit 7 0 bit 15 8 Data 4 Data 5 Data...

Page 710: ...it 7 0 bit 15 8 see descr IF2MCTR see descr IF2MCTR reserved reserved Reset 0x00 Reset 0x00 Reset 0x00 Reset 0x00 Base addr 0x50 IF2 Data A1 IF2 Data A2 Big Endian byte ordering bit 7 0 bit 15 8 bit 7 0 bit 15 8 Data 0 Data 1 Data 2 Data 3 Reset 0x00 Reset 0x00 Reset 0x00 Reset 0x00 Base addr 0x54 IF2 Data B1 IF2 Data B2 Big Endian byte ordering bit 7 0 bit 15 8 bit 7 0 bit 15 8 Data 4 Data 5 Data...

Page 711: ...bit 15 8 bit 7 0 NewDat 32 25 NewDat 24 17 NewDat 16 9 NewDat 8 1 Reset 0x00 Reset 0x00 Reset 0x00 Reset 0x00 Base addr 0x94 Reserved 32 128 Message buffer Base addr 0xA0 Interrupt Pending 2 Interrupt Pending 1 Interrupt Pending is read only bit 15 8 bit 7 0 bit 15 8 bit 7 0 IntPnd 32 25 IntPnd 24 17 IntPnd 16 9 IntPnd 8 1 Reset 0x00 Reset 0x00 Reset 0x00 Reset 0x00 Base addr 0xA4 Reserved 32 128 ...

Page 712: ... is undefined 2 3 CAN Protocol Related Registers These registers are related to the CAN protocol controller in the CAN Core They control the operating modes and the configuration of the CAN bit timing and provide status information CAN Control Register CTRLR res res res res res res res res Bit no Read write R R R R R R R R Default value 0 0 0 0 0 0 0 0 CAN Control Register high byte Address Base 0...

Page 713: ...rite access to the Bit Timing Register while Init 1 bit5 DAR Disable Automatic Retransmission 0 Automatic Retransmission of disturbed messages enabled 1 Automatic Retransmission disabled bit4 res reserved bit bit3 EIE Error Interrupt Enable 0 Disabled No Error Status Interrupt will be generated 1 Enabled A change in the bits BOff or EWarn in the Status Register will generate an interrupt bit2 SIE ...

Page 714: ...eadily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the proceeding of the busoff recovery sequence Status Register STATR res res res res res res res res Bit no Read write R R R R R R R R Default value 0 0 0 0 0 0 0 0 Status Register high byte Address Base 0x02H 15 14 13 12 11 10 9 8 STATRH BOff EWarnEPassRxOK TxOK LEC Bit no Read write R R R R W R W R ...

Page 715: ... been success fully received independent of the result of acceptance bit3 TxOk Transmitted a Message Successfully 0 Since this bit was reset by the CPU no message has been successfully trans mitted This bit is never reset by the CAN Core 1 Since this bit was last reset by the CPU a message has been successfully error free and acknowledged by at least one other node transmitted bit2 bit0 LEC Last E...

Page 716: ...message or acknowledge bit or active error flag or overload flag the device wanted to send a dominant level data or identifier bit logical value 0 but the monitored Bus value was recessive During busoff recovery this status is set each time a sequence of 11 recessive bits has been monitored This enables the CPU to monitor the proceeding of the busoff recovery sequence indicating the bus is not stu...

Page 717: ... Receive Error Counter Actual state of the Receive Error Counter Values between 0 and 127 bit7 bit0 TEC7 0 Transmit Error Counter Actual state of the Transmit Error Counter Values between 0 and 255 res TSeg2 TSeg1 Bit no Read write R R W R W R W R W R W R W R W Default value 0 0 1 0 0 0 1 1 Bit Timimg Register high byte Address Base 0x06H 15 14 13 12 11 10 9 8 BTRH SJW BRP Bit no Read write R W R ...

Page 718: ...han the value programmed here is used bit7 6 SJW Re Synchronisation Jump Width 0x0 0x3 Valid programmed values are 0 3 The actual interpretation by the hardware of this value is such that one more than the value programmed here is used bit5 bit0 BRP Baud Rate Prescaler 0x00 0x3F The value by which the oscillator frequency is divided for generating the bit time quanta The bit time is built up from ...

Page 719: ...dominant CAN_RX 0 1 The CAN bus is recessive CAN_RX 1 bit6 bit5 Tx1 0 Control of CAN_TX pin 00 Reset value CAN_TX is controlled by the CAN Core 01 Sample Point can be monitored at CAN_TX pin 10 CAN_TX pin drives a dominant 0 value 11 CAN_TX pin drives a recessive 1 value bit4 LBack Loop Back Mode 0 Loop Back Mode is disabled 1 Loop Back Mode is enabled bit3 Silent Silent Mode 0 Normal operation 1 ...

Page 720: ...e RAM allowing both processes to be interrupted by each other Figure 2 3 gives an overview of the two Interface Register sets Each set of Interface Registers consists of Message Buffer Registers controlled by their own Command Registers The Command Mask Register specifies the direction of the data transfer and which parts of a Message Object will be transferred The Command Request Register is used...

Page 721: ...ase 0x14 IF1 Mask 2 CAN Base 0x44 IF2 Mask 2 CAN Base 0x16 IF1 Mask 1 CAN Base 0x46 IF2 Mask 1 CAN Base 0x18 IF1 Arbitration 2 CAN Base 0x48 IF2 Arbitration 2 CAN Base 0x1A IF1 Arbitration 1 CAN Base 0x4A IF2 Arbitration 1 CAN Base 0x1C IF1 Message Control CAN Base 0x4C IF2 Message Control CAN Base 0x20 CAN Base 0x32 IF1 Data A1 CAN Base 0x50 CAN Base 0x62 IF2 Data A1 CAN Base 0x22 CAN Base 0x30 I...

Page 722: ...to the IFx Command Request Register bit14 bit8 res Reserved Bits bit5 bit0 Message Number for 32 message buffer CANs 0x00 Not a valid Message Number interpreted as 0x20 0x01 0x20 Valid Message Number the Message Object in the Message RAM is selected for data transfer 0x21 0x3F Not a valid Message Number interpreted as 0x01 0x1F bit7 bit0 Message Number for 128 message buffer CANs 0x00 Not a valid ...

Page 723: ...bject addressed by the Command Request Register bit6 Mask Access Mask Bits 0 Mask bits unchanged 1 Transfer Identifier Mask MDir MXtd to Message Object bit5 Arb Access Arbitration Bits 0 Arbitration bits unchanged 1 Transfer Identifier Dir Xtd MsgVal to Message Object bit4 Control Access Control Bits 0 Control Bits unchanged 1 Transfer Control Bits to Message Object bit3 CIP Clear Interrupt Pendin...

Page 724: ...7 to Message Object bit6 Mask Access Mask Bits 0 Mask bits unchanged 1 Transfer Identifier Mask MDir MXtd to IFx Message Buffer Register bit5 Arb Access Arbitration Bits 0 Arbitration bits unchanged 1 Transfer Identifier Dir Xtd MsgVal to IFx Message Buffer Register bit4 Control Access Control Bits 0 Control Bits unchanged 1 Transfer Control Bits to IFx Message Buffer Register bit3 CIP Clear Inter...

Page 725: ...byte Msk15 8 Bit no Read write R W R W R W R W R W R W R W R W Default value 1 1 1 1 1 1 1 1 IFx Mask 1 Register high byte Address Base 0x16H Base 0x46H 15 14 13 12 11 10 9 8 IFxMSK1H Msk7 0 Bit no Read write R W R W R W R W R W R W R W R W Default value 1 1 1 1 1 1 1 1 Address Base 0x17H Base 0x47H 7 6 5 4 3 2 1 0 IFxMSK1L IFx Mask 1 Register low byte MsgVal Xtd Dir ID28 24 Bit no Read write R W ...

Page 726: ...addresses 0x32 0x62 Data 1 Data 0 IFx Message Data B2 addresses 0x34 0x64 Data 7 Data 6 IFx Message Data B1 addresses 0x36 0x66 Data 5 Data 4 ID15 8 Bit no Read write R W R W R W R W R W R W R W R W Default value 0 0 0 0 0 0 0 0 IFx Arbitration 1 Register high byte Address Base 0x1AH Base 0x4AH 15 14 13 12 11 10 9 8 IFxARB1H ID7 0 Bit no Read write R W R W R W R W R W R W R W R W Default value 0 0...

Page 727: ...bject is no longer required Note If the UMask bit is set to one the Message Object s mask bits have to be programmed during initialization of the Message Object before MsgVal is set to one Message Object UMask Msk28 0 MXtd MDir EoB NewDat MsgLst RxIE TxIE IntPnd RmtEn TxRqst MsgVal ID28 0 Xtd Dir DLC3 0 Data0 Data1 Data2 Data3 Data4 Data5 Data6 Data7 MsgVal Message Valid 0 The Message Object is ig...

Page 728: ...For details on the concatenation of Message Objects see chapter 4 13 Configuration of a FIFO Buffer on page 728 1 The 29 bit extended Identifier will be used for this Message Object MXtd Mask Extended Identifier 0 The extended identifier bit IDE has no effect on the acceptance filtering 1 The extended identifier bit IDE is used for acceptance filtering Dir Message Direction 0 Direction receive On ...

Page 729: ...nd will be set after a successful transmission of a frame IntPnd Interrupt Pending 0 This message object is not the source of an interrupt 1 This message object is the source of an interrupt The Interrupt Identifier in the Interrupt Regis ter will point to this message object if there is no other interrupt source with higher priority RmtEn Remote Enable 0 At the reception of a Remote Frame TxRqst ...

Page 730: ...er INTR Function of the Interrupt Register INTR For 32 message buffer CANs For 128 message buffer CANs IntId15 0 Interrupt Identifier the number here indicates the source of the interrupt 0x0000 No interrupt is pending 0x0001 0x0020 Number of Message Object which caused the interrupt 0x0021 0x7FFF unused 0x8000 Status Interrupt 0x8001 0xFFFF unused IntId15 0 Interrupt Identifier the number here in...

Page 731: ... can check for which Message Object a Transmission Request is pending The TxRqst bit of a specific Message Object can be set reset by the CPU via the IFx Message Interface Registers or by the Message Handler after reception of a Remote Frame or after a successful transmission 0x8001 0xFFFF unused TxRqst32 1 Transmission Request Bits of all Message Objects 0 This Message Object is not waiting for t...

Page 732: ...ten into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU 1 The Message Handler or the CPU has written new data into the data portion of this Message Object NewDat32 25 Bit no Read write R R R R R R R R Default value 0 0 0 0 0 0 0 0 New Data Register 2 high byte Address Base 0x90H 15 14 13 12 11 10 9 8 NEWDT2H NewDat24 17 Bit no Read w...

Page 733: ...ewDat48 41 NewDat40 33 NEWDT 6 5 NewDat 96 65 address 0x98 NewDat96 89 NewDat88 81 NewDat80 73 NewDat72 65 NEWDT 8 7 NewDat 128 97 address 0x9C NewDat128 121 NewDat120 113 NewDat112 105 NewDat104 97 IntPnd32 1 Interrupt Pending Bits of all Message Objects 0 This message object is not the source of an interrupt IntPnd32 25 Bit no Read write R R R R R R R R Default value 0 0 0 0 0 0 0 0 Int Pending ...

Page 734: ...f an interrupt addr 0 addr 1 addr 2 addr 3 INTPND 4 3 IntPnd 64 33 address 0xA4 IntPnd64 57 IntPnd56 49 IntPnd48 41 IntPnd40 33 INTPND 6 5 IntPnd 96 65 address 0xA8 IntPnd96 89 IntPnd88 81 IntPnd80 73 IntPnd72 65 INTPND 8 7 IntPd 128 97 address 0xAC IntPnd128 121 IntPnd120 113 IntPnd112 105 IntPnd104 97 MsgVal32 25 Bit no Read write R R R R R R R R Default value 0 0 0 0 0 0 0 0 Message Valid Regis...

Page 735: ...n overview about the additional flags Table 2 4 Additional flags when more than 32 message buffers exist MsgVal32 1 Message Valid Bits of all Message Objects 0 This Message Object is ignored by the Message Handler 1 This Message Object is configured and should be considered by the Message Handler addr 0 addr 1 addr 2 addr 3 MSGVAL 4 3 MsgVal 64 33 address 0xB4 MsgVal64 57 MsgVal56 49 MsgVal48 41 M...

Page 736: ...ssage transfer Received messages are stored in their appropriate Message Objects if they pass the Message Handler s acceptance filtering The whole message including all arbitration bits DLC and eight data bytes is stored in the Message Object If the Identifier Mask is used the arbitration bits which are masked to don t care may be overwritten in the Message Object The CPU may read or write each me...

Page 737: ... can be set in Silent Mode by programming the Test Register bit Silent to one In Silent Mode the CAN is able to receive valid data frames and valid remote frames but it sends only recessive bits on the CAN bus and it cannot start a transmission If the CAN Core is required to send a dominant bit ACK bit overload flag active error flag the bit is rerouted internally so that the CAN Core monitors thi...

Page 738: ...bined with Silent Mode It is also possible to combine Loop Back Mode and Silent Mode by programming bits LBack and Silent to one at the same time This mode can be used for a Hot Selftest meaning the CAN can be tested without affecting a running CAN system connected to the pins CAN_TX and CAN_RX In this mode the CAN_RX pin is disconnected from the CAN Core and the CAN_TX pin is held recessive Figur...

Page 739: ...sage Object is initiated by writing the Busy bit of the IF2 Command Request Register to 1 the content of the shift register is stored in the IF2 Registers In Basic Mode the evaluation of all Message Object related control and status bits and of the control bits of the IFx Command Mask Registers is turned off The message number of the Command request registers is not evaluated The NewDat and MsgLst...

Page 740: ...ration the CPU is interrupted on certain CAN message and CAN error events 4 2 Message Handler State Machine The Message Handler controls the data transfer between the Rx Tx Shift Register of the CAN Core the Message RAM and the IFx Registers The Message Handler FSM controls the following functions Data Transfer from IFx Registers to the Message RAM Data Transfer from Message RAM to the IFx Registe...

Page 741: ...the Message Valid Register and the TxRqst bits in the Transmission Request Register are evaluated The valid Message Object with the highest priority pending transmission request is loaded into the shift register by the Message Handler and the transmission is started The Message Object s NewDat bit is reset After a successful transmission and if no new data was written to the Message Object NewDat ...

Page 742: ...Dat bit was already set MsgLst is set to indicate that the previous data supposedly not seen by the CPU is lost If the RxIE bit is set the IntPnd bit is set causing the Interrupt Register to point to this Message Object The TxRqst bit of this Message Object is reset to prevent the transmission of a Remote Frame while the requested Data Frame has just been received 4 7 Reception of Remote Frame Whe...

Page 743: ... IFx Data A Register or IFx Data B Register have to be valid before the content of that register is transferred to the Message Object Either the CPU has to write all four bytes into the IFx Data Register or the Message Object is transferred to the IFx Data Register before the CPU writes the new data bytes When only the eight data bytes are updated first 0x0087 is written to the Command Mask Regist...

Page 744: ...f a Remote Frame the CPU may request another CAN node to provide new data for a receive object Setting the TxRqst bit of a receive object will cause the transmission of a Remote Frame with the receive object s identifier This Remote Frame triggers the other CAN node to start the transmission of the matching Data Frame If the matching Data Frame is received before the Remote Frame could be transmit...

Page 745: ...ntrol Register always reflect the status before resetting the bits To assure the correct function of a FIFO Buffer the CPU should read out the Message Objects starting at the FIFO Object with the lowest message number Figure 4 4 shows how a set of Message Objects which are concatenated to a FIFO Buffer can be handled by the CPU Figure 4 4 CPU Handling of a FIFO Buffer 4 16 Handling of Interrupts I...

Page 746: ...sters Page No 714 An interrupt service routine reading the message that is the source of the interrupt may read the message and reset the Message Object s IntPnd at the same time bit ClrIntPnd in the Command Mask Register When IntPnd is cleared the Interrupt Register will point to the next Message Object with a pending interrupt 4 17 Bit Time and Bit Rate The timing parameter of the bit time i e t...

Page 747: ...col Parameter Range Remark BRP 1 32 defines the legth of the time quantum tq Sync_Seg 1 tq fixed length synchronisation of us into system clock Prop_Seg 1 8 tq compensates for the physical delay times Phase_Seg1 1 8 tq may be lengthened temporarily by synchronisation Phase_Seg2 1 8 tq may be shortened temporarily by synchronisation SJW 1 4 tq may not be longer than either Phase Buffer Segment ...

Page 748: ...732 Chapter 34 CAN Controller 4 CAN Application ...

Page 749: ...stopped with software Interrupt Overflow interrupt An interrupt generated when the compare clear register value and the count value of the free run timer match Count value Readable writable write is only possible when the counting stops Others Operates from immediately after reset Free Run Timer to ICU OCU mapping Free run timer 0 and input capture 0 1 co operate Free run timer 1 and input capture...

Page 750: ...CCS bit 7 0 1 From the divider From the outside CLR TCCS bit 2 0 1 No effect Clears the timer CK SCK Pxy z TCCS bit 3 0 1 Disable the clear by the compare match Enable the clear by the compare match Notes When using the input output SCK the external clock CK cannot be used because the port is shared 1 0 General purpose port SCK USART shift clock From the port data register Clear External clock Syn...

Page 751: ...l clock CLKP When using the output compare in order to allow the compare match output and interrupt generation the external clock input of at least 1 clock is required after the compare match bit6 Interrupt request flag When the count value of the free run timer overflows or the clear mode bit MODE is 1 the interrupt request flag is set to 1 if the count values of the free run timer and the compar...

Page 752: ...isters bit4 Stop counting When the count stop bit is set to 1 the free run timer stops When the output compare is being used if the free run timer stops the output compare also stops STOP Operation 0 Enable counting 1 Disable count stop ...

Page 753: ...d writing 1 to the clear bit occurs at the same time the clear bit keeps 1 and after the next time the free run timer is cleared it is cleared bit1 bit0 Count clock division ratio selection when the internal clock is selected Select the division ratio of the count clock of the free run timer Change the division ratio when the setting of the count clock division ratio selection bit is changed When ...

Page 754: ...timer 6 Address 02F8h access Half word Word TCDT7 free run timer 7 Address 02FCh access Half word Word About attributes see Meaning of Bit Attribute Symbols Page No 10 When the timer data register is read the count value of the free run timer is also obtained By writing to the timer data register the timer value can be written in the free run timer When it is written make sure that the free run ti...

Page 755: ... up at the count clock the internal clock divided by n 8 The free run timer counts up at the count clock the external clock synchronized with the internal clock Peripheral clock CLKP Count timing The count of the free run timer Reset The overflow and the interrupt request Clearing the free run timer The count of the free run timer Time FFFFh 0000 h Internal clock FCLKP 2 External pin CKI The count...

Page 756: ...0000 Reset Clear The count of the free run timer Time 0000 h Clear by software or the compare match The enable disable of the operation software Write 0000 Peripheral clock CLKP Count timing N 1 N 0000 0001 Compare value N Compare match Clearing the free run timer The request of interrupt Timing of the clear by the compare match 1 2 3 4 Operation stop Internal clock Operation stop Count value Comp...

Page 757: ...ck See 7 2 Start the count operation See 7 3 In the case of the external clock Set the clock input pin CK as the input Port function register PFRxy z Extra port function register EPFRxy z See 7 2 Table 6 2 Setting Required to Enable the Free run Timer Interrupt Setting Setting Registers Setting Procedures Setting of the free run timer interrupt vector and the free run timer interrupt level See Cha...

Page 758: ... operation bits TCCS STOP Internal clock Setting Count period Clock selection Bit ECLK Count clock bit CLK 1 0 FCLKP 32MHz FCLKP 16MHz To select FCLKP 4 Set to 0 Sets to 00 125 ns 250 ns To select FCLKP 16 Set to 0 Set to 01 0 5 µs 1 µs To select FCLKP 32 Set to 0 Set to 10 1 µs 2 µs To select FCLKP 64 Set to 0 Set to 11 2 µs 4 µs To use the external clock input Setting Pins Count Cycle Free run T...

Page 759: ...4 Interrupt Control Page No 311 about the details of interrupt levels and interrupt vectors Since the interrupt request flag TCCS IVF is not cleared automatically make sure to clear it with software before returning from the interrupt process Write 0 in the IVF bit 7 6 Interrupt Types There is only one type of interrupt and it is generated at the overflow of the free run timer Selection is not req...

Page 760: ...of Free run timer 1 can be used as capture data by ICU2 and ICU3 The value of Free run timer 2 can be used as compare data by OCU0 and OCU1 The value of Free run timer 3 can be used as compare data by OCU2 and OCU3 The value of Free run timer 4 can be used as capture data by ICU4 and ICU5 The value of Free run timer 5 can be used as capture data by ICU6 and ICU7 The value of Free run timer 6 can b...

Page 761: ...e overflow and the compare match of the free run timer is enabled while the free run timer is counting To clear while the free run timer is stopped write 0000H in the timer count data register Write to the timer data register When writing the value in the free run timer make sure to do so while the free run timer is stopped STOP 0 and with word access External clock operation The pulse width requi...

Page 762: ...746 Chapter 35 Free Run Timer 8 Caution ...

Page 763: ...t capture channels 0 1 2 3 4 5 6 7 Compatible timers Input capture channels 0 1 use free run timer 0 Input capture channels 2 3 use free run timer 1 Input capture channels 4 5 use free run timer 4 Input capture channels 6 7 use free run timer 5 Edge Detection Rising falling both edges Interrupt Edge detection Capture value Timer count value 0000H FFFFH Timer Uses free run timer 0 Precision 4 FCLKP...

Page 764: ...on Both edges detection Edge detection polarity Edge detection polarity ICE0 ICS01 bit 4 0 1 Disable interrupts Enable interrupts ICP0 ICS01 bit 6 0 1 Interrupt request not present Interrupt request present WRITE 0 Flag clear Input capture 0 Interrupt 92 Capture data register 1 1 0 Input capture 1 Interrupt 93 IPCP1 CP15 CP0 Edge detection circuit ICU1 P14 1 P14 PFR bit 1 0 1 GP Port ICU input Cap...

Page 765: ...f word Word IPCP6 Input capture 6 Address 02D8h Access Half word Word IPCP7 Input capture 7 Address 02DAh Access Half word Word For information on attributes see Meaning of Bit Attribute Symbols Page No 10 Stores the free run timer 0 count value for the input signal from external pins ICU0 ICU1 using the signal change edge selected by active edge selection bits ICS01 EG 01 00 ICS01 EG 11 10 Input ...

Page 766: ...EG 01 00 is detected on the input from an external pin CS0 the flag becomes 1 To activate the interrupt request the interrupt request permission setting ICE1 1 is necessary If the timing of the interrupt request flag becoming 1 and the writing of 0 occur simultaneously the interrupt request flag will become 1 bit5 Input capture 1 interrupt request permission If input capture 1 interrupt request pe...

Page 767: ... bit0 Input capture 0 active edge selection Select the active capture edge for the input capture signal for external pin ICU0 When the active edge selection bit is 00 input capture 0 is stopped EG11 EG10 Edge selection 0 0 Stop input capture 0 1 Rising edge 1 0 Falling edge 1 1 Both edges rising edge and falling edge EG01 EG00 Edge selection 0 0 Stop input capture 0 1 Rising edge 1 0 Falling edge ...

Page 768: ...nal generated by edge detection synchronous with peripheral clock 3 Store free run timer value in capture register capture 4 Input capture interrupt generation ICU0 ICU1 1 Reset Interrupt request Free run timer 0 count Time FFFFh 0000 h Peripheral clock CLKP Input capture Active edge N N 1 Free run timer 0 N 1 Capture register Interrupt request Input capture 1 2 3 4 N N 1 N 1 N 1 ...

Page 769: ...r capture 9 Input capture interrupt generation 10 Clear interrupt request flag ICS01 ICP0 ICS01 ICP1 in software 11 Detection of input signal falling edge 12 Storage of free run timer value in capture register capture 13 Input capture interrupt generation Reset Free run timer 0 count value Time FFFFh 0000 h Overflow IVF Count value A Count value B Count value C Count value D Interrupt request Inpu...

Page 770: ... Input pin ICU0 ICU7 settings Port function register PFR14 0 PFR14 7 Extra port function register EPFR14 0 EPFR14 7 7 2 Active edge polarity selection for external input Input capture control register ICS01 ICS23 ICS45 ICS67 7 1 Table 6 2 Required Settings for ICU Interrupt Settings Settings register Setting procedure Input Capture interrupt vector Input capture interrupt level settings See Chapte...

Page 771: ...errupt vectors see Chapter 24 Interrupt Control Page No 311 Operation External input active edge polarity bit EG 01 00 EG 11 10 To select rising edge Select 00 To select falling edge Select 10 To select both edges Select 11 Operation Port function PFR14 x Extra Port function EPFR14 x To set it to the external input pins ICU0 Set PFR14 0 to 1 Set EPFR14 0 to 0 To set it to the external input pins I...

Page 772: ...ble interrupts Interrupt request permission interrupt request flag Interrupts are enabled via interrupt request permission bit ICS01 ICE0 ICS01 ICE1 ICS23 ICE0 ICS23 ICE1 ICS45 ICE0 ICS45 ICE1 ICS67 ICE0 ICS67 ICE1 Clearing of interrupt requests is done using interrupt request bit ICS01 ICP0 ICS01 ICP1 ICS23 ICP0 ICS23 ICP1 ICS45 ICP0 ICS45 ICP1 ICS67 ICP0 ICS67 ICP1 Input Capture 6 98 Address 0FF...

Page 773: ... recorded during rising input capture register value x Count clock width of free run timer Example value recorded during falling 2320h Value recorded during rising A635h Overflow frequency 1 count clock 125ns pulse width 2320h 10000h A635h x 125ns 3997 375us Cycle measurement Specify rising or falling for edge detection Detect edge 2 times Cycle Second recorded value input capture register value 1...

Page 774: ...r The value of the input capture register during reset is indeterminate Read out of the input capture register must always be done using 16 or 32 bit access Read modify write Input capture interrupt request bit ICP0 ICP1 will be read as 1 when read with read modify write ...

Page 775: ...utput compare channels 4 5 use free run timer 6 Output compare channels 6 7 use free run timer 7 Operation on compare match Reversal of pin output value toggle output Free run timer clear Interrupt generation Count precision 4 FCLKP 16 FCLKP 32 FCLKP 64 FCLKP dependent on free run timer Toggle change width T 1 x count precision 10000H x count precision Interrupt Compare match interrupt Others Sett...

Page 776: ... OTD1 OCS01 bit9 0 1 Low fixed 1c High fixed Compare operation only writable when stopped CST1 OCS01 bit1 0 1 Disable compare operation Enable compare operation ICE1 OCS01 bit5 0 1 Disable interrupts Enable interrupts CMOD OCS01 bit12 0 OCCP1 match alone inverts OP1 latch External clock for free run timer 2 1 0 0 1 0 OR MODE TCCS0 bit 3 0 1 No clear on compare match Clear on compare match External...

Page 777: ...register 0 OCCP0 OCU1 pin output reverses when free run timer TCDT2 matches compare register 0 OCCP0 or compare register 1 OCCP1 Note Reversal mode does not allow interrupts even with cooperative operation CMOD 1 For output from pins OCU0 OCU1 registers PFR15 0 PFR15 1 must be set bit11 bit10 Undefined Writing does not affect the operation The read value is 1 bit9 Pin level settings output compare...

Page 778: ...al clock as the free run timer operation clock at least one external clock input is necessary after compare match for output compare match output and interrupt generation bit5 Interrupt request enable output compare 1 bit4 Interrupt request enable output compare 0 bit3 bit2 Undefined Writing does not affect the operation The read value is always 1 bit1 Enable operation requests output compare 1 A ...

Page 779: ...son operation between the free run timer count value and the output compare register TCDT0 and OCCP0 Before enabling the operation always set a value to compare register OCCP0 If you stop the free run timer output compare also stops CST0 Operation 0 Disable output compare 0 operation 1 Enable output compare 0 operation ...

Page 780: ...lf word Word OCCP7 Compare 7 Address 02E6h Access Half word Word For information on attributes see Meaning of Bit Attribute Symbols Page No 10 Compares the compare registers OCCP0 OCCP1 to free run timer 2 count value TCD2 Compares the compare registers OCCP2 OCCP3 to free run timer 3 count value TCD3 Compares the compare registers OCCP4 OCCP5 to free run timer 6 count value TCD6 Compares the comp...

Page 781: ...re match 6 Free run timer clear from compare match free run timer 2 7 OCU output level reversal 8 Compare match interrupt request generation 5 6 Peripheral clock CLK BFFEh BFFFh Free run timer 2 Interrupt request BFFFh Compare register value 0001 Compare match signal OCU pin output 0000 7 8 Free run timer 2 clear Interrupt request OCU Output 3 2 Free run timer 0 count Time BFFFh 0000 h BFFFh Compa...

Page 782: ... 8 Free run timer count up 9 Compare 0 match 10 OCU0 output level reversal When CMOD 1 OCU1 output level also reverses 11 Compare 0 match interrupt Free run timer 2 clear Interrupt request 0 OCU0 output 3 2 Free run timer 0 count Time BFFFh 0000h BFFFh Compare register 0 9 4 1 CST 0 7 5 6 4000h Compare register 1 CST 1 4000h OCU1 output OCU0 output OCU1 output CMOD 0 CMOD 1 8 Interrupt request 1 2...

Page 783: ...egister PFR15 0 PFR15 7 Extra port function register EPFR15 0 EPFR15 7 See 7 5 Clear free run timer Timer control register TCCS2 TCCS3 TCCS6 TCCS7 See Chapter 35 Free Run Timer Page No 733 See 7 6 Enable compare operation activate Output control register OCS01 OCS23 OCS45 OCS67 See 7 7 Table 6 2 Item Necessary to Clear the Free run Timer upon Compare match Setting Setting Register Setting Procedur...

Page 784: ...pare register 3 Set OCS23 CMOD bit to 0 To reverse OCU5 output using a compare match from only free run timer 6 and compare register 5 Set OCS45 CMOD bit to 0 To reverse OCU7 output using a compare match from only free run timer 7 and compare register 7 Set OCS67 CMOD bit to 0 To reverse OCU1 output using a compare match from free run timer 2 and compare register 0 as well as free run timer 0 and ...

Page 785: ...et compare 0 pin to L Set OCS01 OTD0 to 0 To set compare 0 pin to H Set OCS01 OTD0 to 1 To set compare 1 pin to L Set OCS01 OTD1 to 0 To set compare 1 pin to H Set OCS01 OTD1 to 1 To set compare 2 pin to L Set OCS23 OTD0 to 0 To set compare 2 pin to H Set OCS23 OTD0 to 1 To set compare 3 pin to L Set OCS23 OTD1 to 0 To set compare 3 pin to H Set OCS23 OTD1 to 1 To set compare 4 pin to L Set OCS45 ...

Page 786: ...trol Page No 311 Operation Port function bit Extra port function bit To set compare 0 pin OCU0 to output Set PFR15 0 bit to 1 Set EPFR15 0 bit to 0 To set compare 1 pin OCU1 to output Set PFR15 1 bit to 1 Set EPFR15 1 bit to 0 To set compare 2 pin OCU2 to output Set PFR15 2 bit to 1 Set EPFR15 2 bit to 0 To set compare 3 pin OCU3 to output Set PFR15 3 bit to 1 Set EPFR15 3 bit to 0 To set compare ...

Page 787: ... the types of interrupts There is only one type of interrupt generated upon a compare match Output Compare 2 102 Address 0FFE64h Interrupt level register ICR43 Address 046Bh Output Compare 3 103 Address 0FFE60h Output Compare 4 104 Address 0FFE5Ch Interrupt level register ICR44 Address 046Ch Output Compare 5 105 Address 0FFE58h Output Compare 6 106 Address 0FFE54h Interrupt level register ICR45 Ad...

Page 788: ...ample A 1024us count clock 125ns Compare 0 value 1024000 2 125 1 4095 FFFh Compare 1 value 1024000 4 125 1 1023 7FFh PWM output Example To output a period A duty 1 4 3 4 L PWM Formula Compare 0 value A count clock Compare 1 value A 4 count clock when duty 1 4 A x 3 4 count clock when duty 3 4 count clock time set with free run timer Note To clear free run timer 0 on compare 0 match setting TCCS0 M...

Page 789: ...are is synchronous with the free run timer so if you stop the free run timer the compare operation also stops Even when reversal mode specification CMOD is set to 1 and the compare operation is in cooperative mode interrupts are generated independently When using an external clock as the free run timer compare matches and interrupts are generated with the following clock To generate compare match ...

Page 790: ...774 Chapter 37 Output Compare 8 Caution ...

Page 791: ...of external event Activation trigger Software trigger Cycle Cycle count clock x reload value 1 Example When count clock 16MHz reload value 15999 Cycle 62 5ns x 15999 1 1 0ms Count active edge When in external event mode choose from 3 types External trigger rising falling both edges Interrupt Request generated by underflow Other 1 Counter stop in software can be reopened Other 2 Control of other pe...

Page 792: ...CU0 P15 0 0 INTE TMCSRx bit3 0 1 UF TMCSRx bit2 0 1 CSL2 0 0 0 1 1 0 1 1 0 0 0 0 0 0 1 1 CLKP 2 CLKP 23 CLKP 25 CLKP 26 TMCSRx bit12 10 1 0 1 CLKP 27 0 0 1 1 1 Reload Timer 0 Internal clock count Software trigger External trigger rising edge External trigger falling edge External trigger both edges Disabled 0 1 0 1 0 1 1 0 1 UF Internal clock CLKP 2 Internal clock Internal clock External event Int...

Page 793: ...start One shot mode Reload mode OUTL 0 0 RELD TMCSR bit5 bit4 1 0 1 1 1 0 Stop Trigger reload counter activation For internal clock see the previous chart Active edge 1 Latch output change 0 Reload INTE TMCSR bit3 0 1 Disable interrupts Enable interrupts 1 Timer interrupt underflow UF TMCSRx bit2 0 1 Underflow not present Underflow generation WRITE 0 Flag clear 0 Reload timer 0 External event coun...

Page 794: ...tes see Meaning of Bit Attribute Symbols Page No 10 bit15 14 Undefined Writing has no effect on the operation The read value is 0 bit13 Undefined reload timer 0 reload timer 2 Always write 0 The read value is 0 bit12 10 Count clock selection CLKP peripheral clock Notes Depending on whether an internal clock or an external event is selected the meaning of the operation mode selection bit MOD 2 0 ch...

Page 795: ... FFFFH causes the count operation to stop bit3 Enable timer interrupt requests When timer interrupt requests are enabled the timer interrupt request flag UF becomes 1 and interrupt requests are generated bit2 Timer interrupt request flag Upon down counter underflow 0000H FFFFH generation the timer interrupt request flag becomes 1 If the MOD2 MOD1 MOD0 Reload trigger 0 0 0 Software trigger 0 0 1 Ex...

Page 796: ...le timer count If timer count is enabled it waits for an activation trigger and when an activation trigger is generated the count operation starts The activation trigger can be a software trigger or an external trigger CNTE Enable timer count 0 Stop count operation 1 Enable count operation waiting for activation trigger ...

Page 797: ...ead out through the timer register TMR Please perform the read out using half word access 4 3 TMRLR Reload register TMRLR0 Reload timer 0 Address 01B0H Access Half word TMRLR1 Reload timer 1 Address 01B8H Access Half word TMRLR2 Reload timer 2 Address 01C0H Access Half word TMRLR3 Reload timer 3 Address 01C8H Access Half word TMRLR4 Reload timer 4 Address 01D0H Access Half word TMRLR5 Reload timer...

Page 798: ... external event trigger 5 Load reload value 6 TOT toggle output start 7 Counter count down internal clock synchronous 8 Generate counter underflow 9 TOT pin output level reversal toggle output 10 Reload reload value 11 Repeat steps 7 to 10 See 8 Caution Page No 794 X X X X X X X X Initial Value RX W RX W RX W RX W RX W RX W RX W RX W Attribute Count clock Activation trigger Soft or external event ...

Page 799: ...ave output during count H output OUTL 0 7 Counter count down internal clock synchronous 8 Generate counter underflow 9 Return TOT pin output level 10 Count stop wait for next activation trigger See 8 Caution Page No 794 FFFF 1 0000 FFFF 1 T CLKP OUTL 0 OUTL 1 TMRLR 1 3 4 5 6 7 8 9 10 2 5 10 Count clock Activation trigger Soft or external event Underflow Output only once Reload data Reload data Dat...

Page 800: ...y 5 Load reload value 6 TOT pin output initial value 7 Counter count down external event synchronous 9 TOT pin output level reversal 10 Reload reload value 11 Repeat steps 6 to 9 See 8 Caution Page No 794 FFFF 1 0000 1 0000 1 T CLKP OUTL 0 OUTL 1 TMRLR 1 2 3 4 5 6 7 8 9 10 5 10 Reload data Load data Reload data Reload register setting value 1 Count start Count Reload data External event clock Acti...

Page 801: ...dog reset software reset will cause the registers in the reload timer to be initialized The initial value of reload registers is indeterminate For detailed information on initial values see the explanation of registers 5 6 Operation during Sleep Mode Even after making the transition to sleep mode the operation of the reload timer will continue 5 7 Operation during Stop Mode When the transition is ...

Page 802: ...OP status Stopped CNTE 0 WAIT 1 WAIT status Waiting for activation trigger CNTE 1 WAIT 1 RUN status Count operation running CNTE 1 WAIT 0 LOAD status Loading value to counter from RUN WAIT TRG 1 or underflow CNTE 1 WAIT 0 Figure 5 1 Status Transition Diagram STOP CNTE 0 WAIT 1 Counter Retains value when stopped Indeterminate after reset Counter Retains value when stopped Indeterminate until load a...

Page 803: ...0 EPFR15 7 See 7 8 Generate activation trigger See 7 10 Soft trigger Software trigger bit setting Reload timer control status TMCSR0 TMCSR7 External trigger Input trigger to TIN pin External input Table 6 2 Settings Necessary for Moving the Reload Timer External Event Operation Setting Setting Registers Setting Procedure Reload value setting Reload TMRLR0 TMRLR7 See 7 1 Count clock selection exter...

Page 804: ...egisters Setting Procedure Reload timer interrupt vector Reload timer interrupt level setting See Chapter 24 Interrupt Control Page No 311 See 7 11 Reload timer interrupt settings Interrupt request clear Enable interrupt requests Reload timer control status TMCSR0 TMCSR7 See 7 12 Table 6 4 Settings Necessary for Stopping the Reload Timer Setting Setting Registers Setting Procedure Reload timer sto...

Page 805: ...vation or simultaneous with activation 7 4 How do I set the reload timer mode reload one shot Use mode selection bit TMCSR RELD 7 5 How do I reverse the output level The settings for the output level are detailed in the following table The setting is done via timer output level bit TMCSR OUTL Count Clock Counter clock selection bit Count clock example CSL2 CSL1 CSL0 When CLKP 32MHz When CLKP 16MHz...

Page 806: ...Timer 7 Q A Reload mode Initial value L level output Set to 0 Reload mode initial value H level output reversed Set to 1 One shot mode counting H level output Set to 0 One shot mode counting L level output reversed Set to 1 ...

Page 807: ...change the port to a TOT pin output 7 9 How do I make the TIN pin into an external event input pin or an external trigger input pin Write 1 to the TIN input selection bits PFR14 to change the port to a TIN pin input Trigger Trigger specification bit MOD 2 0 Software trigger TRG bit set Set to 000 External trigger from TINx pin rising edge Set to 001 External trigger from TINx pin falling edge Set ...

Page 808: ...Interrupt Control Page No 311 Interrupt request flag TMCSR0 UF TMCSR7 UF is not automatically cleared so before returning from interrupt processing set the UF bit to 0 to reset it 7 12 How do I enable interrupts Enabling interrupts interrupt request flag TIN6 pin PFR14 6 1 TIN7 pin PFR14 7 1 Timer Trigger pin Reload timer 0 TIN0 Reload timer 1 TIN1 Reload timer 2 TIN2 Reload timer 3 TIN3 Reload ti...

Page 809: ...errupt request bit TMCSR0 UF TMCSR7 UF 7 13 How do I stop the reload timer This setting is done via the reload timer stop bit See 7 3 How to I enable disable the reload timer count operation Page No 789 Interrupt request permission bit INTE To disable interrupt requests Set to 0 To enable interrupt requests Set to 1 Interrupt request bit UF To disable interrupt requests Set to 0 ...

Page 810: ...G15 internal trigger inputs Reload timer TOT7 output is connected to the A D converter 0 trigger input Rewriting of the count clock selection bit CSL 2 0 operation mode selection bit MOD 2 0 output level setting bit OUTL reload permission bit RELD and timer interrupt request permission bit INTE should be done when the reload timer is stopped TMCSR CNTE 0 The internal prescaler should be already se...

Page 811: ...verted polarity H Clamped output Quantity 4 groups Output 16 channels PPG0 PPG15 Count clock Choose from four choices 1 1 4 1 16 1 64 of the peripheral clock CLKP Period Setting range Duty value 65535 specified with a 16 bit register Period Count clock PCSR register value 1 Example Count clock 32MHz 31 25ns PCSR value 63999 Period 31 25ns 63999 1 2ms Duty Setting range 0 Period value specified wit...

Page 812: ...le as trigger for PPG8 PPG11 Reload timer output 6 TOT6 available as trigger for PPG12 PPG15 Reload timer output 7 TOT7 available as trigger for PPG12 PPG15 External triggers Port GP14_0 ICU0 RLT0 ext trig available as trigger for PPG0 PPG3 PPG8 PP11 Port GP14_1 ICU1 RLT1 ext trig available as trigger for PPG0 PPG3 PPG8 PP11 Port GP14_2 ICU2 RLT2 ext trig available as trigger for PPG0 PPG3 PPG8 PP...

Page 813: ...1 Operation unaffected Software trigger Read Always 0 Selector IRS1 0 PCNL bit3 2 1 Counter borrow or duty match 1 0 Duty match 1 1 Counter borrow 0 0 Software trigger or trigger input available 0 Selector Interrupt cause selection Trigger Borrow Reload timer ch0 Reload timer ch1 EN0 GCN20 bit0 EN1 GCN20 bit1 EN2 GCN20 bit2 EN3 GCN20 bit3 EGS1 0 PCNL bit7 6 Both edges Falling edge Rising edge Oper...

Page 814: ...798 Chapter 39 Programmable Pulse Generator 3 Configuration Note For more information about the ICR register and interrupt vector see Chapter 24 Interrupt Control Page No 311 ...

Page 815: ... PPG12 Address 0332h Access Half word PCSR13 PPG13 Address 033Ah Access Half word PCSR14 PPG14 Address 0342h Access Half word PCSR15 PPG15 Address 034Ah Access Half word See Meaning of Bit Attribute Symbols Page No 10 for details of the attributes The PPG Period Setting registers are buffered Transfers from the buffers to the counter take place automatically at counter overflow or underflow After ...

Page 816: ...f word See Meaning of Bit Attribute Symbols Page No 10 for details of the attributes The PPG Duty Setting registers registers are buffered Transfers from the buffers to the counter take place automatically at counter overflow or underflow Set a value smaller than the setting of PPG Period Setting register PCSR in a PPG Duty Setting register See 8 Caution Page No 821 If the same value as set in PPG...

Page 817: ... Half word PCN14 PPG14 Address 0346h Access Byte Half word PCN15 PPG15 Address 034Eh Access Byte Half word See Meaning of Bit Attribute Symbols Page No 10 for details of the attributes O Rewritable x Not writable See 8 Caution Page No 821 Bit 15 Timer enable operation This bit enables the operation of the PPG Bit 14 Software trigger When the Software Trigger bit is set to 1 a software trigger is g...

Page 818: ...ted with the Trigger Specification bits GCN10 15 12 GCN10 11 8 GCN10 7 4 and GCN10 3 0 of PPG3 to PPG0 GCN11 15 12 GCN11 11 8 GCN11 7 4 and GCN11 3 0 of PPG7 to PPG4 GCN12 15 12 GCN12 11 8 GCN12 7 4 and GCN12 3 0 of PPG11 to PPG8 GCN13 15 12 GCN13 11 8 GCN13 7 4 and GCN13 3 0 of PPG15 to PPG12 using the Trigger Input Edge Selection bit EGS 1 0 Bit 5 Interrupt request enable Bit 4 interrupt request...

Page 819: ...alue is indeterminate Bit 0 PPG output polarity specification When the PPG Output Mask Selection bit PCN PGMS has been set to 1 if the Output Polarity Specification bit OSEL is set to 0 the output is clamped at L if the Output Polarity Specification bit is set to 1 the output is clamped at H 1 Interrupt request The operation is unaffected by writing IRS1 IRS0 Selection 0 0 Software trigger or trig...

Page 820: ...specification GCN12 Bits 11 8 TSEL2 3 0 PPG10 trigger specification GCN12 Bits 7 4 TSEL1 3 0 PPG9 trigger specification GCN12 Bits 3 0 TSEL0 3 0 PPG8 trigger specification PPG4 PPG7 GCN11 Bits 15 12 TSEL3 3 0 PPG7 trigger specification GCN11 Bits 11 8 TSEL2 3 0 PPG6 trigger specification GCN11 Bits 7 4 TSEL1 3 0 PPG5 trigger specification GCN11 Bits 3 0 TSEL0 3 0 PPG4 trigger specification PPG0 PP...

Page 821: ... 7 What activation triggers are available and how are they selected Page No 815 TSEL Activation trigger specification 0 0 0 0 EN0 bit GCN2 register 0 0 0 1 EN1 bit GCN2 register 0 0 1 0 EN2 bit GCN2 register 0 0 1 1 EN3 bit GCN2 register 0 1 0 0 16 bit reload timer 0 2 4 6 0 1 0 1 16 bit reload timer 1 3 5 7 1 0 0 0 External trigger 0 4 1 0 0 1 External trigger 1 5 1 0 1 0 External trigger 2 6 1 0...

Page 822: ...N trigger inputs EN0 EN1 EN2 EN3 is selected with the trigger specification bits GCN11 TSEL0 3 0 GCN11 TSEL1 3 0 GCN11 TSEL2 3 0 and GCN11 TSEL3 3 0 of PPG4 PPG5 PPG6 PPG7 then the selected EN serves as a PPG trigger input bit If any of the EN trigger inputs EN0 EN1 EN2 EN3 is selected with the trigger specification bits GCN12 TSEL0 3 0 GCN12 TSEL1 3 0 GCN12 TSEL2 3 0 and GCN12 TSEL3 3 0 of PPG8 P...

Page 823: ...PTMR10 PPG10 Address 0160h Access Half word PTMR11 PPG11 Address 0168h Access Half word PTMR12 PPG12 Address 0330h Access Half word PTMR13 PPG13 Address 0338h Access Half word PTMR14 PPG14 Address 0340h Access Half word PTMR15 PPG15 Address 0348h Access Half word See Meaning of Bit Attribute Symbols Page No 10 for details of the attributes The count of the 16 bit down counter can be read Be sure t...

Page 824: ... to buffers 6 Counter down count 7 The down counter equals the duty value 8 Inverses the PPG pin output level 9 Counter down count 10 Counter borrow 11 Clear the PPG pin output level return to normal 12 Reload the cycle value 13 Reload the duty value 14 Steps from 6 to 13 are iterated See 8 Caution Page No 821 PPG pin output Interrupt cause Effective edge Duty match Counter borrow Activation trigg...

Page 825: ...tivation trigger 5 Load the cycle and duty values 6 Counter down count 7 Down counter value and duty value 8 Inverse the PPG pin output level 9 Counter down count 10 Counter borrow 11 Clear the PPG pin output level return to normal 12 The operating sequence is now completed See 8 Caution Page No 821 PPG pin output Interrupt cause Effective edge Duty match Counter borrow Activation trigger CNTE Loa...

Page 826: ... available in one shot operation If a restart is not available the second and subsequent triggers have no effect in both PWM and one shot operations The second and subsequent triggers following a shutdown of the down counter are functional Trigger Rising edge detection m n 0 PPG N Restarted by the trigger T Trigger Rising edge detection m n 0 PPG N T Restarted by the trigger ...

Page 827: ... GCN10 GCN11 GCN12 GCN13 7 7 Output polarity specification 7 8 PPG pin output setting Port functions PFR16 PFR17 7 9 Trigger generation software trigger Reload timer GCN2 EN bit PPG Control Status PCN00 PCN15 7 10 See Chapter 38 Reload Timer Page No 775 General Control 2 GCN20 GCN21 GCN22 GCN23 Table 6 2 Settings Needed to Stop the PPG Setting Setting Registers Setting Procedure PPG stop bit setti...

Page 828: ...o the section indicated by the number PPG interrupt cause selection Generate an activation trigger borrow and duty match PPG control status PCN00 PCN15 7 13 PPG interrupt setting Clear interrupt requests Enable interrupt requests 7 14 Table 6 4 Settings Needed to Implement PPG Interrupts ...

Page 829: ...set a cycle following the setting of a cycle See 8 Caution Page No 821 7 2 How do I enable or disable PPG operations Enabling the PPG operation Use the PPG operation enable bit PCN CNTE Enable PPG operation before starting the PPG See 8 Caution Page No 821 7 3 How do I set the PPG operation mode PWM operation one shot operation Operation mode selection Use the mode selection bit PCN MDSE See 8 Cau...

Page 830: ...FFFFh CLKP 0 0 32MHz 62 5ns 2 048µs CLKP 4 0 1 8MHz 250ns 8 192µs CLKP 16 1 0 2MHz 1µs 32 76ms CLKP 64 1 1 500kHz 4µs 131 0ms PPG Pin Output PPG Output Polarity Specification Bit OSEL Setting Procedure To clamp the L level under normal polarity When 0 Set the PPG Output Mask Selection bit PGMS to 1 To clamp the H level under normal polarity When 0 Period value PCSR Set a duty value PDUT To clamp t...

Page 831: ...r PPG0 PPG1 PPG2 PPG3 External Trigger Specification Bit TSEL0 3 0 TSEL1 3 0 TSEL2 3 0 TSEL3 3 0 To select the external trigger on GP14_0 Set 1000 Set 1000 Set 1000 Set 1000 To select the external trigger on GP14_1 Set 1001 Set 1001 Set 1001 Set 1001 To select the external trigger on GP14_2 Set 1010 Set 1010 Set 1010 Set 1010 To select the external trigger on GP14_3 Set 1011 Set 1011 Set 1011 Set ...

Page 832: ... Set 1001 Set 1001 Set 1001 Set 1001 To select the external trigger on GP14_2 Set 1010 Set 1010 Set 1010 Set 1010 To select the external trigger on GP14_3 Set 1011 Set 1011 Set 1011 Set 1011 Internal Trigger PPG12 PPG13 PPG14 PPG15 Internal Trigger Specification Bit TSEL0 3 0 TSEL1 3 0 TSEL2 3 0 TSEL3 3 0 To select the EN0 bit of the GCN23 register Set 0000 Set 0000 Set 0000 Set 0000 To select the...

Page 833: ... 2 1 PPG2 Output specification bit PPG2 PPG3 pin Port Function register PFR17 3 1 PPG3 Output specification bit PPG3 PPG4 pin Port Function register PFR17 4 1 PPG4 Output specification bit PPG4 PPG5 pin Port Function register PFR17 5 1 PPG5 Output specification bit PPG5 PPG6 pin Port Function register PFR17 6 1 PPG6 Output specification bit PPG6 PPG7 pin Port Function register PFR17 7 1 PPG7 Outpu...

Page 834: ...r input bit can be specified with the PPG trigger specification bits to activate all the PPGs simultaneously when the trigger is generated Even if an activation trigger is generated before the operation of a PPG is enabled that PPG would not be activated Be sure to enable the operation of a PPG before generating a trigger to activate it See 7 2 How do I enable or disable PPG operations Page No 813...

Page 835: ...pt Level register ICR51 Address 0473h PPG7 119 Address 0FFE20h PPG8 120 Address 0FFE1Ch Interrupt Level register ICR52 Address 0474h PPG9 121 Address 0FFE18h PPG10 122 Address 0FFE14h Interrupt Level register ICR53 Address 0475h PPG11 123 Address 0FFE10h PPG12 124 Address 0FFE0Ch Interrupt Level register ICR54 Address 0476h PPG13 125 Address 0FFE08h PPG14 126 Address 0FFE04h Interrupt Level regist...

Page 836: ...the interrupt request enable bit PCN IREN to enable interrupts Use the interrupt request bit PCN IRQF to clear interrupt requests See 8 Caution Page No 821 Interrupt Cause Interrupt Cause Setting Bit IRS 1 0 Software trigger or Internal trigger generation PPG0 PPG15 Set 00 Down counter borrow cycle match Set 01 Duty match Set 10 Down counter borrow cycle match or Duty match Set 11 Interrupt Reques...

Page 837: ...o 1 before or concurrently with the activation to enable the PPG operation The values of mode MDSE restart enable RTRG count clock CKS 1 0 trigger input edge EGS 1 0 interrupt cause IRS internal trigger TSEL and output polarity specification OSEL may not be changed while the PPG is operating If any of these values has been changed while the PPG was operating disable the operation of the PPG before...

Page 838: ...822 Chapter 39 Programmable Pulse Generator 8 Caution ...

Page 839: ...ulator 1 PFM Overview The 16 bit pulse frequency modulator consists of two 16 bit down counters two 16 bit reload registers prescalers for generating the internal count clocks and control registers Functions Two independent programmable 16 bit down counters generating low and high pulses The input clock can be selected from prescaled internal clocks the machine clock divided by 2 8 32 64 128 separ...

Page 840: ...CSL0 10 9 MOD1 8 Name 15 INV 14 13 Register P0TMCSR RELD 4 INTE 3 UF 2 CNTE 1 TRG 0 7 6 5 Register structure Control status register 15 0 15 0 P0TMR P0TMRLR 16 bit counter register 16 bit reload register CSL2 12 CSL1 11 CSL0 10 9 MOD1 8 Name 15 INV 14 13 Register P1TMCSR RELD 4 INTE 3 UF 2 CNTE 1 TRG 0 7 6 5 Register structure Control status register 15 0 15 0 P1TMR P1TMRLR 16 bit counter register...

Page 841: ...lear prescaler Internal clock 16 R BUS Reload 8 16 3 φ φ φ φ φ 21 23 25 26 27 GATE CSL2 CSL1 RELD INTE UF CNTE TRG 16 bit down counter Clock selector 16 bit reload register UF 16 Reload 8 16 GATE RELD INTE UF CNTE TRG IRQ 16 bit down counter 16 bit reload register UF CSL0 Clear prescaler Internal clock 3 φ φ φ φ φ 21 23 25 26 27 CSL2 CSL1 Clock selector CSL0 Pulse Gen OUT INV ...

Page 842: ...rol Status Register Functions of the P0TMCSR P1TMCSR bits Bit 15 Reserved Always set to 0 Bit 14 INV INVersion The output signal inversion bit 0 is default level counter 0 high level counter 1 low level 1 inverts the output signal counter 0 low level counter 1 high level Remark Writing INV of P0TMCSR or INV of P1TMCSR or both has the same effect Bit 13 Reserved Always set to 0 Bits 12 10 CSL2 CSL1...

Page 843: ...ion stops when an underflow occurs due to the counter value changing from 0000H to FFFFH Bit 3 INTE The interrupt request enable bit When INTE is 1 an interrupt request is generated when the UF bit changes to 1 When INTE is 0 no interrupt requests are generated Bit 2 UF The counter interrupt request flag UF is set to 1 when an underflow occurs when the counter value changes from 0000H to FFFFH Wri...

Page 844: ...only valid when CNTE 1 Writing 1 has no effect if CNTE 0 16 bit Counter Register P0TMR P1TMR Reading this register reads the count value of the 16 bit counter The initial value is indeterminate Always read this register using 16 bit data transfer instructions P0TMR P1TMR structure Figure 2 2 Structure of the 16 bit Counter Register 16 bit Reload Register P0TMRLR P1TMRLR The 16 bit reload register ...

Page 845: ...ter 40 Pulse Frequency Modulator 2 Reload Counter Registers P0TMRLR P1TMRLR structure Figure 2 3 Structure of the 16 bit Reload Register Access 0 W Address 15 Initial value 0000 0176H W W W W W W W W 0000 017AH ...

Page 846: ...f peripheral clock machine cycle is required from the counter start trigger being input until the reload register data is loaded into counter Counter activation and operation timing Figure 3 1 Counter Activation and Operation Timing Underflow Operation An underflow occurs when the counter value changes from 0000H to FFFFH Therefore an underflow occurs after reload register setting 1 counts If the ...

Page 847: ... in the control register and the internal WAIT signal The available states are CNTE 0 and WAIT 1 STOP state operation halted CNTE 1 and WAIT 1 WAIT state waiting for a trigger and CNTE 1 and WAIT 0 RUN state operating Figure 3 3 shows the transitions between each state Count clock Count clock Underflow set Counter When RELD 1 Data load Counter Reload data 1 1 1 Underflow set When RELD 0 0000H 0000...

Page 848: ...r access Counter Stores the value when counting stopped Indeterminate after a reset Counter Stores the value when counting stopped Indeterminate after a reset until loaded Counter Running Load contents of the reload register to the counter Load complete CNTE 0 CNTE 1 CNTE 1 CNTE 0 TRG 0 TRG 1 TRG 1 TRG 1 RELD UF STOP WAIT RUN CNTE 0 WAIT 1 CNTE 1 WAIT 1 CNTE 1 WAIT 0 LOAD RELD UF CNTE 1 WAIT 0 ...

Page 849: ... set up with RELD 0 Counter 0 should then be started by software trigger TRG 1 By starting counter 0 a high level is generated at the output At the underflow condition of counter 0 counter 1 is automatically reloaded and started by the internal trigger falling edge set MOD1 1 for both counters and a low level is generated at the output At the underflow condition of counter 1 counter 0 is automatic...

Page 850: ...834 Chapter 40 Pulse Frequency Modulator 4 PFM Operation and Setting ...

Page 851: ... triggered by the rising edge of a BIN pin signal Up Down Counter counts up or down depending on the AIN pin signal level Phase difference count mode Multiply by 4 Counting is triggered by the rising edge of AIN and BIN pin signals Up Down Counter counts up or down depending on the ZIN pin signal level Count Source Internal clock Timer mode Peripheral clock CLKP divided by 2 or 8 External trigger ...

Page 852: ...ode WRITE 0 Flag clear Peripheral clock CLKP Prescaler CLKP divided by 2 CLKP divided by 8 From port data register From port data register From port data register Others Enable UDC Others Enable UDC Others Enable UDC Read from port Read from port Read from port Edge detection Edge detection Disable edge detection Enable falling edge detection Enable rising edge detection Enable both edge detection...

Page 853: ...E 0 Flag clear Peripheral clock CLKP Prescaler CLKP divided by 2 CLKP divided by 8 From port data register From port data register From port data register Others Enable UDC Others Enable UDC Others Enable UDC Read from port Read from port Read from port Edge detection Edge detection Disable edge detection Enable falling edge detection Enable rising edge detection Enable both edge detection Gate Ac...

Page 854: ...stops CDCF UDCC0 bit14 0 1 No change direction Direction changed CFIE UDCC0 bit 13 0 1 Disable interrupts Enable interrupts CLKS UDCC0 bit 12 0 1 CLKP divided by 2 CLKP divided by 8 16 bit mode M16E UDCC0 bit15 1 16 bit mode OR OR Up Down Counter Read only Reload compare register Write only Reload 1 1 0 0 1 0 UDF1 0 UDCS0 bit 1 0 No input 0 0 1 1 0 1 1 0 Countdown Countup Both countdown and countu...

Page 855: ...tion Figure 3 5 Register List Note For ICR registers and interrupt vectors refer to Chapter 24 Interrupt Control Page No 311 Figure 3 6 Register List Note For ICR registers and interrupt vectors refer to Chapter 24 Interrupt Control Page No 311 ...

Page 856: ...o 1 on counting up following the reset To enable interrupt requests the interrupt request permission bit must be set CFIE 1 bit13 Enable count direction change interrupt request When the interrupt request permission bit is set to 1 the interrupt request flag CDCF is enabled bit12 Select internal prescaler 15 14 13 12 11 10 9 8 bit M16E Reserved CDCF CFIE CLKS CMS1 CMS0 CES1 CES0 UDCCH 0 0 0 0 0 0 ...

Page 857: ...he reload enable bit is set to 1 the reload compare value RCR is transferred to Up Down Counter UDCR when Up Down Counter is underflowed bit3 Clear UDCR bit2 Select counter clear gate CMS1 CMS0 Count mode 0 0 Timer mode Countdown 0 1 Up down count mode 1 0 Phase difference count mode Multiply by 2 1 1 Phase difference count mode Multiply by 4 CES1 CES0 Edge selection 0 0 Disable edge detection 0 1...

Page 858: ...ction level selection When the counter clear function is selected CGSC 0 When the gate function is selected CGSC 1 0 0 Disable edge detection Disable level detection Disable count 0 1 Detect a falling edge Detect a L level 1 0 Detect a rising edge Detect a H level 1 1 Disable setting Disable setting ...

Page 859: ...nterrupt request permission bit must be set CITE 1 bit3 Overflow detection flag To enable interrupt requests the interrupt request permission bit must be set UDIE 1 bit2 Underflow detection flag 7 6 5 4 3 2 1 0 bit CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0 0 0 0 0 0 0 0 0 Initial value R W R W R W R W0 R W0 R W0 R WX R WX Attribute CSTR Count operation 0 Disable count operation 1 Enable count operat...

Page 860: ...er 4 Register To enable interrupt requests the interrupt request permission bit must be set UDIE 1 bit1 0 Up down flag UDF1 UDF0 Previous count operation 0 0 No input 0 1 Count down 1 0 Count up 1 1 Both of count up and count down ...

Page 861: ...ad by half word access 8 Bit Mode M16E 0 In the 8 bit mode this register functions as a 8 bit up down counter register 0 and a 8 bit up down counter register 1 UDCR1 Up Down Counter 1 Address 00302H Access Byte Half word UDCR0 Up Down Counter 0 Address 00303H Access Byte Half word UDCR3 Up Down Counter 3 Address 00312H Access Byte Half word UDCR2 Up Down Counter 2 Address 00313H Access Byte Half w...

Page 862: ...de be sure to write by half word access 8 Bit Mode M16E 0 In the 8 bit mode this register functions as 8 bit reload compare register 0 and 8 bit reload compare register 1 UDCR1 reload compare 1 Address 00300H Access Byte Half word UDCR0 reload compare 0 Address 00301H Access Byte Half word UDCR3 reload compare 3 Address 00310H Access Byte Half word UDCR2 reload compare 2 Address 00311H Access Byte...

Page 863: ...847 Chapter 41 Up Down Counter 4 Register 1 Stop counting 2 Write a value to the reload compare register 3 Write 1 to the counter write bit CCR CTUT ...

Page 864: ...lue is reloaded to Up Down Counter 6 The software clears the underflow flag 7 The software enables interrupts 8 Up Down Counter counts down 9 An underflow occurs An interrupt request has been made 10 The software clears the underflow flag 11 Repeat 8 to 10 CLKS RLDE CGSC CSTR 1 2 8 7 6 5 4 3 3 9 9 10 FCLKP divided by 2 FCLKP divided by 8 Reload value Countdown Interrupt request Reload value Reload...

Page 865: ...inuous pulse input to the AIN pin causes Up Down Counter to count up 9 When pulse input to the AIN pin stops Up Down Counter stops counting 10 When pulse input to the BIN pin is detected Up Down Counter counts down 11 The count direction change flag is set to 1 12 Continuous pulse input to the BIN pin causes Up Down Counter to count down 13 Up Down Counter is underflowed and the underflow flag is ...

Page 866: ... 6 When pulse input to the AIN pin stops Up Down Counter stops counting 7 When a pulse input to the BIN pin is detected Up Down Counter counts down 8 When counting is disabled at the ZIN pin Up Down Counter stops counting 9 Neither pulse input to the AIN pin nor counting at the ZIN pin being enabled Up Down Counter neither counts up nor down 10 Counting is enabled at the ZIN pin 11 Up Down Counter...

Page 867: ...nditions When the voltage level at the AIN pin detected on the rising edge at the BIN pin is H When the voltage level at the AIN pin detected on the falling edge at the BIN pin is L Count down Conditions When the voltage level at the AIN pin detected on the rising edge at the BIN pin is L When the voltage level at the AIN pin detected on the falling edge at the BIN pin is H When this count mode is...

Page 868: ...pin is L When the voltage level at the BIN pin detected on the falling edge at the AIN pin is H Count down Conditions When the voltage level at the AIN pin detected on the rising edge at the BIN pin is L When the voltage level at the AIN pin detected on the falling edge at the BIN pin is H When the voltage level at the BIN pin detected on the rising edge at the AIN pin is H When the voltage level ...

Page 869: ...r a clear request Compare match ZIN edge detection and writing 0 to the clear bit DCC is made the counter is cleared when counting is disabled CSTR 0 4 When Up Down Counter exceeds the maximum count the overflow flag is set to 1 and the counter value is returned to 0000 0066 H 0065 H 0066 H 0000 H Clear request Countup Clear timing 0001 H Count value Compare value 0066 H 0065 H 0066 H 0065 H Count...

Page 870: ... occur at the same time clear takes precedence 5 8 Writing a Value to Counter 1 Counting of Up Down Counter is disabled 2 A value is written to PCR 3 1 is written to the count write bit CTUT 4 A value is transferred from the reload compare register RCR to Up Down Counter Countdown Reload timing 0066 H Underflow 0001 H 0066 H 0064 H 0000 H 0065 H Count value Compare value RCR Up Down Counter CSTR C...

Page 871: ... gate using the ZIN pin See 7 9 and 7 10 Activate Up Down Counter Count status register UDCS See 7 11 Table 6 2 Required Settings to Run Up Down Counter in Up Down Count Mode Setting Setting registers Setting procedure Set the reload value compare value Reload compare register UDRC See 7 16 Optional Set a value to Up Down Counter Or Clear the count value of Up Down Counter Reload compare register ...

Page 872: ...ply by 2 or 4 See 7 2 Enable clearing of Up Down Counter at the time of the counting following a compare match See 7 6 Enable reloading at the time of underflow See 7 7 Enable count control clear gate using the ZIN pin See 7 9 and 7 10 Activate Up Down Counter Count status register UDCS See 7 11 Table 6 4 Required Settings for Up Down Counter Interrupt Setting Setting registers Setting procedure S...

Page 873: ...hen the counter counts up Use the up down counter clear enable bit UDCC UCRE Up Down Counter s bit length 16 bit mode enable bit M16E To set the bit length to 8 Set the bit to 0 To set the bit length to 16 bit Set the bit to 1 Count mode Count mode selection bit CMS 1 0 To set the count mode to timer Set the bit to 00 To set the count mode to up down count Set the bit to 01 To set the count mode t...

Page 874: ...ear gate bit UDCC CGSC and counter clear gate edge select bits UDCC CGE 1 0 These settings are enabled for all the count modes GCE 1 0 11 indicates that setting is disabled When the count up value agrees with the compare value Reload enable bit RLDE To disable reloading of the reload value RCR to Up Down Counter Set the bit to 0 To enable reloading of the reload value RCR to Up Down Counter Set th...

Page 875: ...d Use the compare detection flag UDCS CMPF Regardless of counter operations counting up down or a value being set or reloaded the compare detection flags are set to 1 when the count value agrees with the compare value When the count up value agrees with the compare value Count activate bits UDCS CSTR To disable Up Down Counter s count operation Set the bit to 0 To enable Up Down Counter s count op...

Page 876: ...on UDCS CMPF Overflow UDCS OVFF Underflow UDCS UDFF So the software must write 0 to the interrupt request flag before control is returned from interrupt processing 7 18 What interrupts are available and how are they selected There are three interrupt causes Count direction change compare match overflow underflow An interrupt request is made by ORing these three interrupt causes each interrupt caus...

Page 877: ... request permission bits UDCS CITE Overflow underflow interrupt request permission bits UDCS UDIE To clear interrupt requests use the following interrupt request bits For count direction changes UDCC CDCF For compare detection UDCS CMPF For overflow UDCS OVFF For underflow UDCS UDFF Interrupt request permission bits CFIE CITE and UDIE To disable interrupt requests Set the bit to 0 To enable interr...

Page 878: ...ith the compare value during both counting up and down These flags are also set to 1 when The reload value is reloaded to Up Down Counter or The Up Down Counter s count value agrees with the compare value when Up Down Counter is activated The Up Down Counter s count value is cleared by a clear request which is generated On the edge of a signal input from the ZIN pin By writing 0 to the up down cou...

Page 879: ...bes the register structure and functions and describe the operation of the Sound Generator The Sound Generator consists of the Sound Control register Frequency Data register Ampli tude Data register Decrement Grade register Tone Count register Sound Disable register PWM pulse generator Frequency counter Decrement counter and Tone Pulse counter ...

Page 880: ...r Prescaler S1 S0 Amplitude Data register CO EN PWM DEC CLKP Tone Pulse Counter EN CO CI Tone Count register Decrement Counter EN CO CI Decrement Grade register Frequency Counter EN CO Frequency register CI Toggle flip flop EN D Q reload 1 d reload DEC TONE Mix SGA SGO INTE INT ST IRQ S2 ...

Page 881: ...tial value Frequency Data register Address 00019AH 15 14 13 12 11 10 9 8 D7 D6 D5 D4 D3 D2 D1 D0 SGAR R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 Bit number Read write Initial value Amplitude Data register Address 00019CH R W 0 R 0 0 R W 7 6 5 4 3 2 1 0 SGDR Bit number Read write Initial value Decrement Grade register Address 00019FH 15 14 13 12 11 10 9 8 SGTR R W R W R W R W R W R W X X X X X...

Page 882: ...matic decrement of the sound in conjunction with the Decrement Grade register If this bit is set to 1 the stored value in the Amplitude Data register is decremented by 1 one every time when the Decrement counter counts the number of tone pulses from the toggle flip flop specified by the Decrement Grade register bit 5 TONE Tone output bit When this bit is set to 1 the SGO signal becomes a simple sq...

Page 883: ...FR The Frequency Data register stores the reload value for the Frequency counter The stored value represents the frequency of the sound or the tone signal from the toggle flip flop The register value is reloaded into the counter at every transition of the toggle signal The following figure shows the relationship between the tone signal and the register value It should be noted that modifications o...

Page 884: ...the stored value in the Amplitude Data register is decremented by 1 one at the end of the tone cycle This operation realizes automatic decrement of the sound with fewer number of CPU interventions It should be noted that the number of the tone pulses specified by this register equals to register value 1 When the Decrement Grade register is set to 00 the decrement operation is performed every tone ...

Page 885: ...e counter is connected to the carry out signal from the Decrement counter And when the Tone count register is set to 00 the Tone Pulse counter sets the INT bit every carry out from the Decrement counter Thus the number of accumulated tone pulses is Decrement Grade register 1 x Tone Count register 1 i e When the both registers are set to 00 the INT bit is set every tone cycle ...

Page 886: ...870 Chapter 42 Sound Generator 3 Registers ...

Page 887: ...of two PWM pulse generators Block Diagram of Stepping Motor Controller Figure 1 1 Stepping Motor Controller with A D Converter Function Remark The SMC channels 0 1 2 and 3 are shared with ADC inputs PWM2 pulse generator PWM1 pulse generator CK EN PWM PWM1 compare register PWM1 selection register Selector Output enable PWM1P PWM1M Output enable PWM2P load BS PWM2M Selector CK EN PWM PWM2 compare re...

Page 888: ... register PWM2 Compare register PWM1 Selection register PWM2 Selection register PWM2 pulse generator PWM1 pulse generator CK EN PWM PWM1 compare register PWM1 selection register Selector Output enable PWM1P PWM1M Output enable PWM2P load BS PWM2M Selector CK EN PWM PWM2 compare register PWM2 selection register P25 3 SMC2M4 P25 2 SMC2P4 P25 1 SMC1M4 P25 0 SMC1P4 Port 25 PWM control register PFR25 C...

Page 889: ...Address PWM1 Compare register PWC10 PWC11 PWC12 PWC13 PWC14 PWC15 Address PWM1 Selection register PWS10 PWS11 PWS12 PWS13 PWS14 PWS15 0x0C1 0x0C3 0x0C5 0x0C7 0x0C9 0x0CB Address PWM Control register PWC0 PWC1 PWC2 PWC3 PWC4 PWC5 P2 0x092 0x09A 0x0A2 0x0AA 0x0B2 0x0BA 0x093 0x09B 0x0A3 0x0AB 0x0B3 0x0BB 0x090 0x098 0x0A0 0x0A8 0x0B0 0x0B8 0x091 0x099 0x0A1 0x0A9 0x0B1 0x0B9 0x096 0x09E 0x0A6 0x0AE ...

Page 890: ...PWM1 pulse generator starts in order to reduce the switching noise generated by the output driver When the CE bit is cleared to 0 during operation of the PWM pulse generator the generator is initialized to stop operating bit 2 SC 8 10 bits switching bit When 1 is set to the SC bit the PWM pulse generator operates at 10 bit When 0 is set to the SC bit the P2 P1 P0 Clock input PWM cycle at Fcp 32 MH...

Page 891: ...875 Chapter 43 Stepper Motor Controller 2 Registers PWM pulse generator operates at 8 bit bit 1 to 0 Reserved bits Always set the reserved bits to 00 ...

Page 892: ...ter 1 is set to the BS bit of the PWM2 selection register When 0 is set to SC bit of the PWM control register and PWM performs 8 bit operation the D9 and D8 bits are undefined value Be sure to perform half word access to the PWM1 2 compare registers bit 15 to 10 Reserved bit Always set the reserved bit to 0 bits 9 to 0 D9 to D0 Compare data These bits are used to set the PWM pulse width PWM2 Compa...

Page 893: ...or Controller 2 Registers Figure 2 1 Relationship between the Compare Register Setting Value and PWM Pulse Width One PWM cycle 256 1024 input cycles Register value 000H 80H 200H FFH 3FFH 128 512 input cycle 255 1023 input cycle ...

Page 894: ...omatically by software simultaneously the BS bit is set to 1 no change is made to the BS bit and the automatic clearing is cancelled When 0 is set to the BS bit and is being cleared automatically by software simultaneously the BS bit is cleared to 0 however the PWM pulse generator and the selector are not load the values of the registers at the end of the current PWM cycle Note When the BS bit equ...

Page 895: ...h 3FFh 000h PWM 1 cycle PWM pulse PWM pulse generator compare register value PWM pulse generator counter value XXXh 200h Load the values of the registers and reflected in the output signal 3FFh PWM compare register value BS PWM pulse PWM pulse generator compare register value PWM pulse generator counter value PWM compare register value BS PWM pulse PWM pulse generator compare register value PWM pu...

Page 896: ... reserved bit to 0 bit 5 to 3 P2 to P0 Output select bits These bits are used to select the output signal for SMC1P bit 2 to 0 M2 to M0 Output select bits These bits are used to select the output signal for SMC1M The table below shows the relationship between the output levels and the select bits m 1 to 2 motor coils n 0 to 5 stepper motor channels P2 P1 P0 PWMmPn M2 M1 M0 PWMmMn 0 0 0 L 0 0 0 L 0...

Page 897: ...the counter starts incrementing from 00H on the selected count clock rising The PWM output pulse wave remains H until the value of the counter matches the value set to PWM compare register and then changes to and remains L until the value of the counter overflows FFH 00H Figure 3 2 Examples of PWM1 2 Waveform Output shows the PWM waveform generated by the PWM generator PWM1 H width compare value i...

Page 898: ...current PWM cycle The BS bit is to be cleared automatically to 0 at the beginning of the next PWM cycle When 1 is written to the BS bit and the BS bit is cleared to 0 simultaneously at the beginning of the next PWM cycle 1 is written to the BS bit and clearing of the BS bit is cancelled Table 3 1 Selection of Motor Drive Signals and Setting of PWM Selection Registers 1 2 P2 P1 P0 Bits PWM2P Output...

Page 899: ...PWM or to change the PWM output 1 must be written to the BS bit of the PWM2 selection register after or and at the same time a setting is written to those registers the PWM compare register 1 2 and the PWM selection register 1 2 When 1 is set to the BS bit the new setting is enabled at the end of the current PWM cycle and the BS bit is cleared automatically Also when 1 is written to the BS bit and...

Page 900: ...884 Chapter 43 Stepper Motor Controller 4 Caution ...

Page 901: ...annel Scan conversion mode continuous conversion of multiple channels programmable for up to 32 channels Single conversion mode Convert the specified channel only once Continuous mode Repeatedly convert the specified channels Stop mode Convert one channel then temporarily halt until the next activation Enables synchronization of the conversion start timing A D conversion can be followed by an A D ...

Page 902: ...er AVSS AVRH L AVCC CLKP Ope rating Cloc k ADC S 0 1 input c irc uit AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 MP X D A conve rte r Sample Hold circuit Comparator De c ode r A D data re giste r Dat a bus A D control re gister 0 A D control re gister 1 ATGX 16 bit Re load Time r P re sc ale r...

Page 903: ...s 01A4h Access Half word Byte See Meaning of Bit Attribute Symbols Page No 10 for details of the attributes 15 14 13 12 11 10 9 8 Bit ADE31 ADE30 ADE29 ADE28 ADE27 ADE26 ADE25 ADE24 0 0 0 0 0 0 0 0 Initial value R W R W R W R W R W R W R W R W Attribute 7 6 5 4 3 2 1 0 Bit ADE23 ADE22 ADE21 ADE20 ADE19 ADE18 ADE17 ADE16 0 0 0 0 0 0 0 0 Initial value R W R W R W R W R W R W R W R W Attribute 15 14 ...

Page 904: ...s Page No 10 for details of the attributes ADSCH ADC0 Address 01AAh Access Word Half word Byte See Meaning of Bit Attribute Symbols Page No 10 for details of the attributes 7 6 5 4 3 2 1 0 Bit MD1 MD0 S10 ACH4 ACH3 ACH2 ACH1 ACH0 0 0 0 0 0 0 0 0 Initial value R W R W R W R R R R R Attribute 15 14 13 12 11 10 9 8 Bit D9 D8 0 0 0 0 0 0 X X Initial value R0 R0 R0 R0 R0 R0 R R Attribute 7 6 5 4 3 2 1 ...

Page 905: ...le RST clears them to 0 Be sure to set start channel and end channel to 1 7 6 5 4 3 2 1 0 Bit ANE4 ANE3 ANE2 ANE1 ANE0 0 0 0 0 0 Initial value RX W0 RX W0 RX W0 R W R W R W R W R W Attribute 15 14 13 12 11 10 9 8 Bit ADE31 ADE30 ADE29 ADE28 ADE27 ADE26 ADE25 ADE24 0 0 0 0 0 0 0 0 Initial value R W R W R W R W R W R W R W R W Attribute 7 6 5 4 3 2 1 0 Bit ADE23 ADE22 ADE21 ADE20 ADE19 ADE18 ADE17 A...

Page 906: ... Initialized to 0 by a reset If DMA is used this bit is cleared at the end of DMA transfer bit 5 INTE Interrupt enable This bit is enables or disables the conversion completion interrupt Cleared by a reset bit 4 PAUS A D converter pause This bit is set when A D conversion temporarily halts The A D converter has only one register to store the conversion result Therefore the previous conversion resu...

Page 907: ...mode restarting is not occurred Check BUSY bit before writing 1 Activate conversion after clearing Do not specify forcible termination and software activation BUSY 0 and STRT 1 at the same time bit 0 reserved bit Always write 0 to this bit A D control status register 0 ADCS0 ADCS0 ADC0 Address 01A5h Access Half word Byte See Meaning of Bit Attribute Symbols Page No 10 for details of the attributes...

Page 908: ... case resolution is 8 bit and the conversion result is stored to ADCR0 Initialized to 0 by a reset bit 4 to 0 ACH4 0 Analog convert select channel These bits show current converted channel Initialized to 0000 by reset 3 3 Data Register ADCR1 ADCR0 These registers store the conversion results of the A D converter ADCR0 stores lower 8 bit ADCR1 stores upper ACH4 ACH3 ACH2 ACH1 ACH0 Converted channel...

Page 909: ...ue of this register during A D conversion operation Sampling timer setting register ADCT ADCT1 ADC0 Address 01A8h Access Word Half word Byte See Meaning of Bit Attribute Symbols Page No 10 for details of the attributes ADCT0 ADC0 Address 01A9h Access Word Half word Byte See Meaning of Bit Attribute Symbols Page No 10 for details of the attributes bit 15 to 10 CT5 0 A D conversion time set These bi...

Page 910: ...o be set that sampling time is over Tsamp ex CLKP 32MHz AVCC 4 5V Rext 200K Tsamp 200 103 2 52 103 10 7 10 12 7 15 17 us ST 15 17 6 31 25 9 485 44 ST has to be set over 486D 111100110B Tsamp is decided by Rext Thus conversion time should be considered together with Rext 3 5 A D Channel Setting Register ADSCH ADECH These registers specify the channels for the A D converter to convert Do not update ...

Page 911: ... Initialized to ANS 00000 ANE 00000 by a reset ex Channel Setting ANS 30ch ANE 3ch single conversion mode Operation Conversion channel 30ch 31ch 0ch 1ch 2ch 3ch end bit 12 to 8 ANS4 0 Analog start channel set bit 4 to 0 ANE4 0 Analog end channel set 7 6 5 4 3 2 1 0 Bit ANE4 ANE3 ANE2 ANE1 ANE0 0 0 0 0 0 Initial value RX W0 RX W0 RX W0 R W R W R W R W R W Attribute ANS4 ANE4 ANS3 ANE3 ANS2 ANE2 ANS...

Page 912: ...ats the process continuously When the start and end channels are the same ANS ANE conversion is performed continuously for that channel ex ANS 00000b ANE 00011b Start AN0 AN1 AN2 AN3 AN0 repeat ANS 00010b ANE 00010b Start AN2 AN2 AN2 repeat In continuous mode conversion is repeated until 0 is written to the BUSY bit Writing 0 to the BUSY bit forcibly stops the conversion operation Note that forcib...

Page 913: ... 6 Conversion end INT flag set BUSY flag clear 7 Buffers the conversion value Buffered data storage 8 Software based INT flag clear Channel selection Activation trigger AN input Internal level Conversion value Conversion a Conversion b Conversion c Sample hold Buffer ADT Conversion end INT BUSY Flag clear A D conversion activation or software 1 2 3 4 5 6 7 8 Flag clear on A D conversion activation...

Page 914: ...ersion b conversion c b Conversion end c Buffers the conversion value 5 AN1 conversion 6 AN2 conversion 7 AN3 conversion 8 INT flag set BUSY flag clear 9 Next A D activation 10 INT flag clear BUSY flag set Scan start channel selection Activation trigger AN input Buffers Conversion end INT BUSY AN1 AN2 AN3 ADT0 ADT1 ADT2 ADT3 a b c AN0 AN1 AN2 AN3 AN0 6 5 4 3 2 1 7 8 9 10 AN1 conversion value AN2 c...

Page 915: ...apter 38 Reload Timer Page No 775 External trigger Inputs a trigger to the ADTG 0 1 pin External input Conversion end flag check A D control ADCS See 7 8 Conversion value read Data buffers ADCR See 7 9 Table 5 2 Settings needed to use A D Scan Conversion Mode Setting Setting Registers Setting Procedure Mode selection Scan conversion A D control ADCS See 7 1 Bit length selection See 7 2 Starting ch...

Page 916: ...ing Registers Setting Procedure Forced stop A D control ADCS See 7 10 Table 5 4 Items needed to enable A D Interrupts Setting Setting Registers Setting Procedure A D interrupt vector and A D interrupt level settings See Chapter 24 Interrupt Control Page No 311 See 7 11 A D interrupt cause selection A D conversion end A D control registers ADCS See 7 12 A D interrupt setting Clear interrupt request...

Page 917: ... 1 0 6 2 How do I specify a bit length Configure the conversion result storage bit length setting ADCS S10 MD1 MD0 Operating mode 0 0 Single mode all restarts conversion during operation enabled 0 1 Single mode restarts conversion during operation disabled 1 0 Continuous mode restarts conversion during operation disabled 1 1 Stop mode restarts conversion during operation disabled Operation Mode Co...

Page 918: ...ext Thus conversion time should be considered together with Rext 6 4 How do I enable analog pin input Use Port Function register PFR and Extra Port Function register EPFR Operation PFR setting EPFR setting To program the AN0 pin as an input PFR29 0 1 EPFR29 0 0 To program the AN1 pin as an input PFR29 1 1 EPFR29 1 0 To program the AN2 pin as an input PFR29 2 1 EPFR29 2 0 To program the AN3 pin as ...

Page 919: ...pin as an input PFR26 2 1 EPFR26 2 1 To program the AN27 pin as an input PFR26 3 1 EPFR26 3 1 To program the AN28 pin as an input PFR26 4 1 EPFR26 4 1 To program the AN29 pin as an input PFR26 5 1 EPFR26 5 1 To program the AN30 pin as an input PFR26 6 1 EPFR26 6 1 To program the AN31 pin as an input PFR26 7 1 EPFR26 7 1 Operation PFR setting EPFR setting To program the AN16 pin as an input for SMC...

Page 920: ...st bits ADCS INT Checking the Operation Verification bits ADCS BUSY 6 9 How do I read a conversion value The conversion value can be read from Data Buffer register ADCR 6 10 How do I force an A D conversion operation to a stop Use the Forced Stop bits ADCS BUSY The operation of the A D is unaffected by writing 1 to the Forced Stop bit BUSY To specify a software trigger Set 00 To specify an externa...

Page 921: ...n bit is available 6 13 How do I enable disable clear interrupts Interrupt Request Enable flag Interrupt Request flag Interrupts are enabled using the Interrupt Request Enable bits ADCS INTE Interrupt request are cleared using the Interrupt Request bits ADCS INT See 7 Caution Page No 906 Interrupt Vector Default Interrupt Level Setting Bit ICR 4 0 AD0 134 Address 0FFDE4h Interrupt Level register I...

Page 922: ... circuit to receive the voltage present on the analog input pin in the sample hold capacitor after the activation of an A D conversion Therefore if the analog input external circuit has a high output impedance it may happen that analog input voltage fails to get stabilized within the sampling cycle For this reason keep the output impedance of the external circuit sufficiently low If the output imp...

Page 923: ...t transit from 000 H to 001 H VVFST Voltage at which digital output transit from 3FE H to 3FF H Digital output N Linearity error VNT 1LSB N 1 VOT LSB 1LSB Digital output N Differential linearity error V N 1 T VNT 1 LSB 1LSB VNT Voltage at which digital output transit from N 1 to N 3FF 3FE 3FD 004 003 002 001 VOT Measurement value Ideal characteristics Actual conversion characteristics VNT Measurem...

Page 924: ...SS V 1024 VOT Ideal value AVSS 0 5LSB V VFST Ideal value AVRH 1 5LSB V Overall error of digital output N VNT 1LSB N 1 0 5LSB 1LSB VNT Voltage at which digital output transit from N 1 to N 0 5LSB 1 5LSB 3FF 3FE 3FD 004 003 002 001 Ideal characteristics Actual conversion characteristics Actual conversion characteristics VNT Measurement value 1LSB N 1 0 5LSB AVss AVRH Digital output Analog input Over...

Page 925: ...d R 2R type conversion Quantity 2 Output DA0 pin and DA1 pin Conversion time 0 45us Typ Load capacitance 20pF 2 0us Typ Load capacitance 100pF Resolution 10 bit resolution Output range From AVSS 0V to 1023 1024 x AVCC Interrupt None Others Power down feature available fixed 0 V output Useful for saving current consumption when in sleep mode D A Analog output Pin D A converter Digital value ...

Page 926: ... List 2 2 2 2R 2 2 D A converter 0 1 DA0 P28 6 DA1 P28 7 DADR0 DADR1 DA0 DA1 PFR28 bit 6 PFR28 bit 7 0 1 General purpose port output D A output only 1 0 DAE 0 1 D A output disable 0 V output D A output enable DACR bit 0 DACR bit 1 AVss AVcc From Port Data register Port read Register number bit Data Control Port function DADR0 DACR DAE0 PFR28 6 DADR1 PFR28 7 D A 0 1 Pin DA0 DA1 R R R R R R R 2 R DA...

Page 927: ...bit0 D A output control Enables a converted analog level to be output from the DA pin To place the DA0 pin in the output state it is necessary to set PFR28 6 1 The D A output equals 0 0 V when the D A output control bit is 0 bit1 D A output control Enables a converted analog level to be output from the DA pin To place the DA1 pin in the output state it is necessary to set PFR28 7 1 The D A output ...

Page 928: ...912 Chapter 45 D A Converter 4 Registers bit2 D A 8 10 bit mode control In case MD08 1 the 8 bit value of DA7 DA0 DADR 7 0 is output MD08 Operation 0 D A resolution is 10 bits 1 D A resolution is 8 bits ...

Page 929: ...ware programmable 2 D A conversion in progress 3 Output enabled software programmable 4 Analog value output 5 Digital value rewrite software programmable 6 D A conversion in progress 7 Output level finalized 8 Output disabled software programmable 9 Fixed 0 V output A0h 60h 1 2 3 4 5 6 7 8 9 DADR0 DADR1 DAE DA0 DA1 output level 0A0h 060h ...

Page 930: ...mber Table 6 1 Settings Needed to Use D A Setting Setting Registers Setting Procedure Digital value settings D A Data Registers DADR See 7 1 Pin settings Port Function Register PFR28 7 PFR28 6 See 7 2 Output enabled D A Control Registers DACR See 7 3 Table 6 2 Settings Needed to Stop D A Output Setting Setting Registers Setting Procedure Output halted D A Control Registers DACR See 7 3 ...

Page 931: ...nable or disable D A output Use the D A output control bits DACR DAE0 DACR DAE1 O V AVss is output when disabled This is functional even while in a stopped state 7 4 How do I activate a D A conversion A conversion begins on writing a digital value See 7 1 7 5 What is the formula used to work out the value necessary to produce an expected voltage Equation Value V Expected analog value x 1024 AVCC T...

Page 932: ...e of a power supply within the limits of Recommended Power Supply Operation Conditions in the chapter entitled 2 Instruction for Users Page No 3 is recommended DADR Settings D A Converter Output Voltage Value 000H 0V AVss 0 0V 001H 1 1024 x AVCC V 002H 2 1024 x AVCC V 3FDH 1021 1024 x AVCC V 3FEH 1022 1024 x AVCC V 3FFH 1023 1024 x AVCC V When stopped 0V Avss 0 0V DADR Settings D A Converter Outpu...

Page 933: ...Under Overvoltage De tection describes the register structure and functions and describes the operation of the Alarm Comparator 2 Block Diagram Figure 2 1 Alarmcomparator simplified circuit A C S R AVDD OUT1 OUT2 PD CLKP D D Q Q CK CK STOP CLKP IRQ_AC Alarm comparator analog part Alarm comparator digital part Interrupt logic ALARM 0 8 AVDD 0 4 AVDD RST ...

Page 934: ... Alarm comparator OV output Bit 2 IRQ Interrupt bit 1 Fast mode enabled 0 Slow mode enabled Initial value 1 Interrupt enabled in case of overvoltage Initial value 0 No interrupt in case of overvoltage 1 Interrupt enabled in case of undervoltage Initial value 0 No interrupt in case of undervoltage 0 analog input voltage 2 5 AVDD 1 analog input voltage 2 5 AVDD 1 analog input voltage 4 5 AVDD 0 anal...

Page 935: ...terrupt event and can be reset by writing to the ACSR register The ACSR can be polled continuously in order to monitor the input voltage which is feed to the AC comparator inputs 4 3 Setting and Resetting of IRQ Flagbit The IRQ bit of the ACSR register can be reset to zero by writing a 0 to it Writing an 1 to the IRQ bit of ACSR register has no effect IRQ can only be set to 1 by hardware i e by th...

Page 936: ...alog parts will remain undefined for at least 3 us after power on and also after reentering the runmode You have to make sure whether the IRQ is correct set before enabling the alarm comparator interrupt source Table 4 2 Alarm Comparator power down modes STOP PD analog part digital part 0 0 run mode run mode 0 1 power down mode run mode 1 0 power down mode power down mode 1 1 power down mode power...

Page 937: ...Driver Built in for internal divided resistors or external divided resistors can be connected to the V0 V3 pins Data memory Built in 20 byte data memory for display Stop mode Enable LCD display in the sub stop mode Blank display Selectable Pin The SEG0 39 of COM0 4 pin usage can be switched between general and specialized purposes Other External divided resistors can be also used to shut off the c...

Page 938: ...sistors Internal Divided Resistors 0 1 Peripheral clock Sub clock Prescaler VRAM0 VRAM1 VRAM2 VRAM3 VRAM4 VRAM5 VRAM6 VRAM7 VRAM8 VRAM9 VRAM10 VRAM11 VRAM12 VRAM13 VRAM14 VRAM15 SEG32 SEG39 PFR31 0 PFR31 7 0 1 SEG output General purp port SEG24 SEG31 PFR32 0 PFR32 7 SEG16 SEG23 PFR33 0 PFR33 7 SEG8 SEG15 PFR34 0 PFR34 7 SEG0 SEG7 PFR35 0 PFR35 7 COM0 COM3 PFR30 0 PFR30 3 0 1 General purp ports COM...

Page 939: ...923 Chapter 47 LCD Controller 3 Configuration Figure 3 2 Register List ...

Page 940: ... supply To connect external divided resistors the LCD drive power supply control bit VSEL must be set to 0 bit4 Select blanking bit3 2 Select a display mode If the display mode select bit MS 1 0 is set to 00 LCD Controller ceases to operate A L level is output through common segment pins 7 6 5 4 3 2 1 0 bit CSS LCEN VSEL BK MS1 MS0 FP1 FP0 0 0 0 1 0 0 0 0 Initial value R W R W R W R W R W R W R W ...

Page 941: ...anel FP1 FP0 Frame period When peripheral clock is selected When subclock is selected 0 0 FCLKP 213 N FCL SUB 23 N 0 1 FCLKP 214 N FCL SUB 24 N 1 0 FCLKP 215 N FCL SUB 25 N 1 1 FCLKP 216 N FCL SUB 26 N FCLKP Peripheral clock CLKP frequency FCL SUB Subclock frequency N Time division number Selected with the display mode select bits MS1 and MS0 ...

Page 942: ...ss Byte VRAM10 SEG20 SEG21 Address 0F6H Access Byte VRAM11 SEG22 SEG23 Address 0F7H Access Byte VRAM12 SEG24 SEG25 Address 0F8H Access Byte VRAM13 SEG26 SEG27 Address 0F9H Access Byte VRAM14 SEG28 SEG29 Address 0FAH Access Byte VRAM15 SEG30 SEG31 Address 0FBH Access Byte VRAM16 SEG32 SEG33 Address 0FCH Access Byte VRAM17 SEG34 SEG35 Address 0FDH Access Byte VRAM18 SEG36 SEG37 Address 0FEH Access B...

Page 943: ...927 Chapter 47 LCD Controller 4 Registers Correspondence between VRAM and Common Segment Pins ...

Page 944: ...o 11111111B 4 4 LCDCMR Common Pin Switching Register LCDCMR Address 0E8H Access Byte Half word Word For attributes refer to Meaning of Bit Attribute Symbols Page No 10 bit7 Analogue macro control Always set to 0B when LCD is used bit6 4 Undefined Read Indeterminate Write 0 is always written bit3 0 Common driver enable Always set to 1111B when LCD is used 15 14 13 12 11 10 9 8 bit SEGEN9 SEGEN8 0 0...

Page 945: ...on selected waveform 5 This output waveform is a 2 frame AC waveform in accordance with the duty cycle setting and drives LCD 6 When MS 1 0 00 is used to deactivate LCD a L level is output through both common and segment pins 7 If LCD operation is enabled in the sub stop mode LCEN 1 LCD display is displayed Note that frame period generation clock signals must be supplied at this time 8 LCD display...

Page 946: ... V0 V1 V2 V3 V0 V1 V2 V3 V0 V1 V2 V3 SEG 2n output V0 V1 V2 V3 SEG 2n 1 output V0 V1 V2 V3 LCD cell corresponding to SEG 2n COM0 output LCD cell corresponding to SEG 2n COM1 output LCD cell corresponding to SEG 2n 1 COM0 output LCD cell corresponding to SEG 2n 1 COM1 output ON OFF ON OFF ON OFF ON OFF ...

Page 947: ...or LCD display COM3 output is not used Example of 1 3 Bias Output Waveform LCD cells with the maximum voltage difference between common and segment outputs are lit Table 5 2 Example of Data Memory Contents for Display Segment Contents of data memory for display COM3 output COM2 output COM1 output COM0 output SEG 2n output 1 0 0 SEG2n 1 output 1 0 1 ...

Page 948: ... V1 V2 V3 SEG 2n 1 output V0 V1 V2 V3 LCD cell corresponding to SEG 2n COM0 output LCD cell corresponding to SEG 2n COM1 output LCD cell corresponding to SEG 2n COM2 output LCD cell corresponding to SEG 2n 1 COM0 output LCD cell corresponding to SEG 2n 1 COM1 output LCD cell corresponding to SEG 2n 1 COM2 output ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ...

Page 949: ... COM0 output SEG 2n output 0 1 0 0 SEG2n 1 output 0 1 0 1 COM3 output COM0 output COM1 output COM2 output V0 V1 V2 V3 V0 V1 V2 V3 V0 V1 V2 V3 V0 V1 V2 V3 SEG 2n output V0 V1 V2 V3 SEG 2n 1 output V0 V1 V2 V3 LCD cell corresponding to SEG 2n COM0 output LCD cell corresponding to SEG 2n COM1 output LCD cell corresponding to SEG 2n COM2 output LCD cell corresponding to SEG 2n COM3 output LCD cell cor...

Page 950: ...mory VRAM See 7 2 Select the frame period generation clock Set a frame period LCD control register 0 LCR0 See 7 3 Select a duty cycle Activation See 7 4 Enable LCD display See 7 6 Table 6 2 Required Setting to Disable LCD display Setting Setting register Setting procedure Disable blank LCD display LCD control register 0 LCR0 See 7 6 Table 6 3 Required Setting to Deactivate LCD Setting Setting regi...

Page 951: ...OM1 COM1 COM2 COM2 COM3 COM3 SEG0 Port function register PFR35 7 0 SEG0 SEG1 SEG1 SEG2 SEG2 SEG3 SEG3 SEG4 SEG4 SEG5 SEG5 SEG6 SEG6 SEG7 SEG7 SEG8 Port function register PFR34 7 0 SEG8 SEG9 SEG9 SEG10 SEG10 SEG11 SEG11 SEG12 SEG12 SEG13 SEG13 SEG14 SEG14 SEG15 SEG15 SEG16 Port function register PFR33 7 0 SEG16 SEG17 SEG17 SEG18 SEG18 SEG19 SEG19 SEG20 SEG20 SEG21 SEG21 SEG22 SEG22 SEG23 SEG23 SEG2...

Page 952: ...936 Chapter 47 LCD Controller 7 Q A SEG32 Port function register PFR31 7 0 SEG32 SEG33 SEG33 SEG34 SEG34 SEG35 SEG35 SEG36 SEG36 SEG37 SEG37 SEG38 SEG38 SEG39 SEG39 ...

Page 953: ...e following settings are available N Time division number MS 1 0 value 1 Set an appropriate frame period that corresponds to the frame frequency of your LCD panel Pin COM1 COM0 SEG 2n bit 1 bit 0 SEG 2n 1 Bit 5 Bit 4 pin COM2 COM1 COM0 SEG 2n bit 2 bit 1 bit 0 SEG 2n 1 Bit 6 Bit 5 Bit 4 pin COM3 COM2 COM1 COM0 SEG 2n bit 3 bit 2 bit 1 bit 0 SEG 2n 1 bit 7 Bit 6 Bit 5 Bit 4 Frame period Selected va...

Page 954: ...ime division number To deactivate LCD Pin output L Set to 00 N A To set the 1 2 duty cycle output mode Set to 01 2 To set the 1 3 duty cycle output mode Set to 10 3 To set the 1 4 duty cycle output mode Set to 11 4 Controlled operation Blanking select bit BK To enable LCD display Set to 0 To disable blank LCD display Non selected waveform is output through segment pins Set to 1 Controlled operatio...

Page 955: ...nected by setting 0 to the LCD drive power supply control bit LCR0 VSEL 7 10 How do I use external divided resistors to shut off the current when LCD is deactivated The V0 pin is internally connected to Vss GND via a transistor For this reason the current generated on deactivating LCD controller can be shut off by connecting external divided resistors to the V0 pin on the Vss side To shut off the ...

Page 956: ...on your LCD different external divided resistors are used Use appropriate resistor values When the display mode is set to 1 2 duty cycle non selected waveform is output through the COM2 and COM3 pins For 1 3 duty cycle the COM3 pin is used to output non selected waveform Inappropriate selection or setting of frame period generation clock CSS LCD drive power supply control VSEL duty cycle MS 1 0 an...

Page 957: ...nal before it outputs to the terminal thus allowing the clock signal to be used as an event at which external circuits act in synchronization with a MCU function 2 Features Format Divide an internal clock signal to output it to a terminal MONCLK Channel 1 Division ratios CLK 1 CLK 2 CLK 3 CLK 16 Glitch free output enable Programmable mark level output L or H before enabling the clock output Interr...

Page 958: ... RC oscillation Sub clock after SCKS 0101 0110 Main oscillation after CSV Sub oscillation after CSV 0111 1000 Clock modulator output to C Unit Clock modulator observer output 1001 PLL output after 1 g 1010 1011 PLL output after 1 m PLL output after 1 c 1100 1101 PLL input after 1 n CLKB 1110 1111 CLKP CLKT CMPRE3 0 Clock Output Frequency CMCFG bit 7 4 0 0 0 0 0 1 1 1 1 1 0 1 1 0 1 0 0 0 0 1 1 0 1 ...

Page 959: ...ed by 7 0 1 1 1 Source clock selected by CMSEL divided by 8 1 0 0 0 Source clock selected by CMSEL divided by 9 1 0 0 1 Source clock selected by CMSEL divided by 10 1 0 1 0 Source clock selected by CMSEL divided by 11 1 0 1 1 Source clock selected by CMSEL divided by 12 1 1 0 0 Source clock selected by CMSEL divided by 13 1 1 0 1 Source clock selected by CMSEL divided by 14 1 1 1 0 Source clock se...

Page 960: ...r operation See chapter CSCFG Clock Source Configuration Register Page No 196 about information on the additional functions of this register 7 6 5 4 3 2 1 0 bit EDSUEN PLLLOCK RCSEL MONCKI CSC3 CSC2 CSC1 CSC0 0 X 0 0 0 0 0 0 Initial value INIT pin input watchdog reset X X X X X X X X Initial value software reset R W R R W R W R W R W R W R W Attribute MONCKI Function 0 MONCLK mark level is low Ini...

Page 961: ... changes to output L status output H if MONCKI is set to 1 for one period of the internal prescaled clock 4 After one period of the selected and prescaled internal clock MONCLK outputs the selected and prescaled internal clock 5 CMSEL is set from the selected clock to 0000 no clock selected 6 The MONCLK pin changes to output L status output H if MONCKI is set to 1 for one period of the internal pr...

Page 962: ... Clock Monitor Selection CMCFG CMSEL 3 0 See 7 1 Change the mark level Clock Monitor Inverter CSCFG MONCKI See 7 1 Enable clock monitor output MONCLK Clock Monitor Selection CMCFG CMSEL 3 0 See 7 2 See 7 3 Operation CMCFG CMSEL 3 0 To set an output terminal MONCLK Set to the appropriate clock 0000 Clock Division Ratio Output Frequency Example Frequency Prescaler CMCFG CMPRE 3 0 CLKP 32MHz CLKP 40M...

Page 963: ...k source CMCFG3 0 or the prescaler ratio CMPRE3 0 The CMPRE3 0 registers can only be written if the CMCFG3 0 registers are currently 0x0 The CMPRE3 0 registers can only be written if the CMCFG3 0 registers are written to 0x0 within the same write access Between 2 write accesses to CMPRE CMCFG there must be at least 2 cycles of the divided monitor clock ...

Page 964: ...948 Chapter 48 Clock Monitor 8 Caution ...

Page 965: ...operate even in the STOP mode Operational on main clock 4MHz sub clock 32kHz or RC clock 100kHz Quantity 1 Time unit Clock divided by 2 Operation clock For register access CLKP For time count Mainclock Subclock RC clock Time Initial setting and adjustment are possible Interrupt Interrupts can be generated at any of the five intervals 1 half second 1 second 1 minute 1 hour and 1 day Others By chang...

Page 966: ...rflow Overflow WTSR R WTMR R WTHR R OR Prescaler 1 2 INTE1 WTCR bit11 0 1 INTE1 WTCR bit11 0 1 Disable interrupts Enable interrupts Reload Second Counter Minute Counter Hour Counter INT1 WTCR bit10 0 1 Read 1 INT1 WTCR bit10 0 1 Disable Read 1 Interrupt request has been made Read 1 Interrupt request has been made INT2 WTCR bit12 0 1 Read 1 INT2 WTCR bit12 0 1 Disable Disable INTE2 WTCR bit13 0 1 I...

Page 967: ...TE0 INT0 0 0 0 0 0 0 0 0 Initial value 0 0 0 0 0 0 0 0 When reset R W R R1 W R W R R1 W R W R R1 W R W R R1 W Attribute 7 6 5 4 3 2 1 0 bit Reserved Reserved Reserved RUN UPDT ST 0 0 0 0 0 X Initial value 0 0 0 0 0 X When reset R W0 R W0 R W0 RX WX R WX R R0 W RX WX R W Attribute INTE3 Operation 0 No interrupt requests 1 Generate interrupt requests at 1 day 24 hour intervals INT3 Status Read Write...

Page 968: ...ll three bytes make sure the reload operation will not be performed in between the write instructions Otherwise the 21 bit prescaler loads the incorrect value of the combination of new data and old data bytes It is generally INT1 Operation Read Write 0 No interrupt requests Clear the flag 1 Generate interrupt requests at 1 minute intervals Writing does not affect the operation INTE0 Operation 0 No...

Page 969: ...at the second rising edge of the RTC clock after ST has been set to 0 It will rise again at the half second rising edge of RTC clock after ST has been set to 1 If this operation is to be done several times directly after each other wait for RUN to go to high before setting ST to low again WTCER Address 04A1H Access Byte For attributes refer to Meaning of Bit Attribute Symbols Page No 10 bit7 2 Und...

Page 970: ... in the sub second registers corresponds to the time for half a second One second is reached after counting twice the reload value set in WTBR See 7 1 How do I set the count period of 1 second Page No 959 WTBR0 7 6 5 4 3 2 1 0 bit D20 D19 D18 D17 D16 X X X X X Initial value Unchanged Unchanged Unchanged Unchanged Unchanged When reset RX WX RX WX RX WX R W R W R W R W R W Attribute WTBR1 7 6 5 4 3 ...

Page 971: ...ond registers every time when the second counter overflows that is at intervals of one minute When the hour minute second counters are read the saved count values not written ones are read The hour minute second registers consist of two separate sets of registers one for reading and the other for writing See 8 Caution Page No 961 WTHR 7 6 5 4 3 2 1 0 bit H4 H3 H2 H1 H0 X X X X X Initial value Unch...

Page 972: ...o the hour minute second timers 6 The values of the sub second registers WTBR0 WTBR1 WTBR2 are loaded to the 21 bit down counter 7 The run flag RUN is set to 1 8 The 21 bit down counter begins counting at the mainclock divided by 2 4 2 MHz subclock divided by 2 32 768 2 KHz or RC clock divided by 2 100 2 kHz 9 When the 21 bit down counter reaches 000000H the value of the sub second registers is lo...

Page 973: ... up at which the hour counter counts up generating a 1 hour interrupt request 12 When the hour counter counts up to 23 the counter is cleared next time when the counter counts up at which a 1 day interrupt request is generated 14 The software changes the status of Real time Clock to STOP Set the stop bit STCR STOP to 1 Real time Clock continues to operate in the STOP state 17 The device recovers f...

Page 974: ...isters WTHR WTMR WTSR See 7 3 Activate Real time Clock RTC control register WTCR See 7 4 Table 6 2 Required Settings to Know Time Setting Setting Registers Setting Procedure Read time Hour minute second registers WTHR WTMR WTSR See 7 6 Table 6 3 Required Settings to Stop Real Time Clock Setting Setting Registers Setting Procedure Stop Real time Clock RTC control register WTCR See 7 7 Table 6 4 Req...

Page 975: ...ng Use the start bit WTCR ST 7 5 How do I confirm that Real time Clock is active Use the run flag WTCR RUN 7 6 How do I know time Read the hour minute second registers WTHR WTMR WTSR Note that only byte access is allowed to these register So when these registers are read at the very timing of changing over the hour or minute boundary as shown below there is a possibility of misjudging the time So ...

Page 976: ...he corresponding interrupt request enable bit 7 10 How do I enable interrupts Use the interrupt request enable bits WTCR INTE0 WTCR INTE1 WTCR INTE2 WTCR INTE3 and WTCER INTE4 To clear interrupt requests Use the interrupt request bits WTCR INT0 WTCR INT1 WTCR INT2 WTCR INT3 and WTCER INT4 Interrupt vectors Default Interrupt level set bit ICR 4 0 132 0FFDECh Interrupt level register ICR58 047Ah Int...

Page 977: ... Second register is updated while the ST bit is 0 However if this update is done immediately after an RTC second interrupt there should be enough time to securely modify the registers until the next reload operation next second interrupt even if ST is not set to 0 and the module is in operation When updating the registers by using the ST bit the following must be taken into account The new value i...

Page 978: ...en these registers are read at the very timing of changing over the hour or minute boundary as shown below there is a possibility of misjudging the time So read several times to get a logically consistent value Example Read begins at the second register 02 59 59 03 59 59 03 00 00 Read begins at the hour register 02 59 59 02 00 00 03 00 00 In this case the current time should be interpreted as 3 o ...

Page 979: ...Hz clock By utilizing this hardware in conjunction with software processing the accuracy of the 32kHz clock or 100kHz RC clock can come closer to that of the 4MHz clock The measurement result from the Clock Calibration Module can be processed by the software and the setting required for the Real Time Clock Module can be obtained This module consists of two timers one operating with the 32kHz clock...

Page 980: ... CLKP 32 sync 4MHz TIMER UC18TRR CUTR 32kHz TIMER UC18TRD UC18RBI CUTR 24 bit UC18IO UC18BUS RBB RSLEEPB RMWB _WRB _RDB RSTB FC18 CLK32G CUTD RB INT_I CUTD CUTD 16 bit CUCR 3 bit CUTR 24 bit INT_INT set reset reset set reset reset READY RUNSS set STRT async RST INT counter 16 bit READY RST async READY STRT CLKPG2 RSLEEPB RSLEEPB RB RSLEEP RMW _WR _RD RST INT CLKP CLKPG gate gate gate STRT gate STR...

Page 981: ...t 3 Timing 3 Timing Figure 3 1 Timing of the measurement process 4 MHz 32 kHz RUNS RUN CUTD CUTD 1 0 1 CUTD 32 kHz counter 16 bit 2 4 MHz counter 24 bit 0 old CUTR new CUTR CLKP READYPULSE CLKP STRT INT CLKP 32 kHz STRTS 32 kHz READY 32 kHz ...

Page 982: ...TOSC32 OSC100 2 x TOSC4 3 x TCLKP TOSC4 1 2 x TOSC32 OSC100 3 2 x TCLKP TCLKP 1 3 x TOSC32 OSC100 2 3 x TOSC4 The input frequencies must not exceed the values given in Table 4 1 Table 4 1 Maximum operation frequencies Table 4 2 Example of valid clock ratios which fulfill requirements 1 and 2 OSC32 OSC100 OSC4 CLKP maximum 2 MHz 500 ns 10 MHz 100 ns 50 MHz 20 ns OSC32 OSC100 OSC4 CLKP maximum opera...

Page 983: ...libration Unit clock sources STRT INT INTEN Bit no Read write R R R R W R R W R W R W Default value 0 0 0 0 0 0 0 0 Address 0004B0H 7 6 5 4 3 2 1 0 CUCRL Control Register low byte TDD15TDD14 TDD13 TDD12 TDD11TDD10 TDD9 TDD8 Bit no Read write R W R W R W R W R W R W R W R W Default value 1 0 0 0 0 0 0 0 32 100kHz Timer Register high byte Address 0004B2H 15 14 13 12 11 10 9 8 CUTDH TDD7 TDD6 TDD5 TD...

Page 984: ... R R Default value 0 0 0 0 0 0 0 0 Address 0004B7H 7 6 5 4 3 2 1 0 CUTR2L 4MHz Timer Register2 low byte TDR15TDR14 TDR13 TDR12 TDR11TDR10 TDR9 TDR8 Bit no Read write R R R R R R R R Default value 0 0 0 0 0 0 0 0 4MHz Timer Register2 high byte Address 0004B6H 15 14 13 12 11 10 9 8 CUTR2H TDR23 TDR22 TDR21TDR20 TDR19 TDR18 TDR17TDR16 Bit no Read write R R R R R R R R Default value 0 0 0 0 0 0 0 0 Ad...

Page 985: ...tarting a new calibration Otherwise the end of the calibration process is only signalized by the STRT bit the INT flag stays 1 also during calibration BIT 4 STRT Calibration Start When the STRT bit is set to 1 by the software the calibration starts The 32kHz 100kHz Timer starts counting down from the value stored in the 32KHz 100kHz Timer Data Register and the 4MHz Timer starts counting up from ze...

Page 986: ...er Page No 196 how to select between those clocks In order to achieve a measurement duration of 1 second at a 32kHz oscillation the CUTD register has to be load with 0x8000 32768 dec This number results from the exact oscillation frequency of the crystal which is Fosc 32768 Hz The ideal values of the measurement results if a 4 00 MHz crystal is used are shown in the following table In order to ach...

Page 987: ...urement duration The duration of the whole process from writing a 1 into the STRT bit until STRT is reset by hardware is longer than the actual calibration measurement time due to synchronization between the different clock domains Process Duration CUTD 3 Tosc100 The calibration measurement time is exact CUTD Tosc100 duration of calibration CUTD value CUTR value 2 sec 0x0000 0x7A1200 1 75 sec 0xE0...

Page 988: ...ng calibration results in random values The end of calibration is indicated by the INT bit and the STRT bit in CUCR register After these bits changed from 0 to 1 resp 1 to 0 the value of CUTR is valid Writing into this register by software has no effect The 4MHz Timer operates with the 4MHz oscillation clock TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 Bit no Read write R R R R R R R R Default value 0 ...

Page 989: ...d be set in the 100kHz Timer Data Register and it represents 50 000 pulses of the 100kHz oscillation clock This setting should result in the stored value of approximately 1E8480Hex in the 4MHz Time Data Register This value represents 2 000 000 pulses of the 4MHz oscillator Table 6 1 Ideal measurement results CUTR with 32 768kHz and 4 0MHz oscillators The key to the use of the calibration module is...

Page 990: ...n up from RTC mode by software to trigger the calibration measurement every minute and the duration of the calibration is set to 1 second the increase in the power dissipation can be 20xIRTC 60 1 3 IRTC Therefore the software has to make sure that the increase should not affect the hardware limitations coming from the system requirements For example the software has to be designed to trigger the c...

Page 991: ...rupt depending on the supply state of either the internal or external supply voltage 2 Features Generates a low voltage reset or a low voltage interrupt Interrupt activation source can be selected between external supply VDD5 detection and internal supply VDD detection Selectable trigger levels for external and internal supply levels Power down function ...

Page 992: ...VIEN LVIRQ 0 0 0 0 0 0 Initial value INIT pin input watchdog reset X X X X 0 0 Initial value Software reset R0 W0 R W R W R W R W R0 W0 R W R W Attribute LVSEL Function 0 Internal VDD LV detection used for LV Int and LV Reset Initial value 1 External VDD5 LV detection used for LV Int and LV Reset LVEPD Function 0 External VDD5 LV detection active Initial value 1 External VDD5 LV detection power do...

Page 993: ...hardware to the low voltage detection module the register setting is not changed in this case and will be applied next time the main regulator is switched off 7 6 5 4 3 2 1 0 bit LVESEL3 LVESEL2 LVESEL1 LVESEL0 LVISEL3 LVISEL2 LVISEL1 LVISEL0 0 0 0 0 0 1 1 1 Initial value INIT pin input watchdog reset X X X X X X X X Initial value Software reset R W R W R W R W R W R W R W R W Attribute LVESEL3 LV...

Page 994: ...978 Chapter 51 Low Voltage Reset Interrupt 3 Registers ...

Page 995: ...ew Module for controlling the behaviour of the MAIN Regulator and SUB Regulator in the device modes 2 Features Main Regulator enable and disable independently for Sub run and STOP RTC Main regulator standby flag output Selectable Sub regulator output voltage for Sub run and STOP RTC ...

Page 996: ...n Regulator enable in STOP RTC mode Bit0 Main Regulator disable in Subrun Mode 7 6 5 4 3 2 1 0 bit MSTBO MAINKPEN MAINDSBL X X X X X X 0 0 Initial value INIT pin input watchdog reset X X X X X X X X Initial value Software reset R0 WX R0 WX R0 WX R R0 WX R0 WX R W R W Attribute MSTBO Function 0 Main regulator is in RUN mode 1 Main regulator is in STANDBY mode MAINKPEN Function 0 Main regulator disa...

Page 997: ... main regulator on the default level is applied internally by hardware to the Sub Reg ulator the register setting is not changed in this case and will be applied next time the main regulator is switched off 7 6 5 4 3 2 1 0 bit FLASHSEL MAINSEL SUBSEL3 SUBSEL2 SUBSEL1 SUBSEL0 0 0 0 0 0 1 1 0 Initial value INIT pin input watchdog reset X X X X X X X X Initial value Software reset R0 WX R0 WX R W R W...

Page 998: ...982 Chapter 52 Regulator Control 3 Registers ...

Page 999: ...r R4 the Boot Security Vector BSV Vector 144 0x0F FDBC will be checked This check is performed as follows if the data of this vector represents a valid address in the specified address range the Boot Security Vector itself becomes valid If the Boot Security Vector is valid the Boot ROM is left and the user application is started at the address given by this vector The purpose of this feature is to...

Page 1000: ... Chart of checking boot conditions on MB91V460 1 Boot Security Vector points to address in valid address range 0x04 000 0x13 FFFF 2 Start user application at address given by Boot Security Vector 3 Start user application at default user program entry address 4 Timeout about 100 ms ...

Page 1001: ...cation is entered at the address given by BSV1 The Magic Number is used as flag for a valid user application or especially for a user bootloader If you want to re program this user bootloader a second user bootloader which handles the re programming of the first user bootloader has to be located at the address BSV2 points to If BSV2 does not point to a valid address range then application is start...

Page 1002: ...tarted at default user program entry address 0x0F 4000 Flow Chart of checking boot conditions on flash derivates of MB91460 series 1 Boot Security Vector points to address in Flash ROM 2 Magic Number 0x0A897A 3 Start user application at address given by Boot Security Vector 1 2 4 Start user application at default user program entry address 5 Timeout about 100 ms ...

Page 1003: ...READ 1 0x01 2 0x02 Address 4 bytes Size 2 bytes 241 0xF1 130 0x82 Binary Dump CheckSum 2 bytes Lo MidLo MidHi Hi Lo Hi Direct read and dump Bootloader sends 16bit checksum WRITE 1 0x01 3 0x03 Address 4 bytes Size 2 bytes Binary Dump 241 0xF1 131 0x83 CheckSum 2 bytes Lo MidLo MidHi Hi Lo Hi Receive and store dump in RAM Bootloader sends 16bit checksum CALL 1 0x01 4 0x04 Address 4 bytes 241 0xF1 13...

Page 1004: ...rmed Register Value Address Description TBCR 0x03 0x482 Time Base Counter Sync RST Register RSRR 0 see note 0x480 Reset Source Register visible in R4 TBR 0x0FFC00 Table Base Register SP 0x0203F8 Stack Pointer PFR21 0x07 0xD95 Port Function Register Port 21 UART0 SMR00 0x05 0x041 UART0 Mode Register SCR00 0x17 0x040 UART0 Control Register SSR00 0x042 UART0 Serial Status Register RDR00 0x043 UART0 R...

Page 1005: ... parameters are expected in CPU registers R4 and R5 R4 2bits LSB of register for setting the flash access mode b 00 32bit read write mode b 01 16bit read write mode b 1x 64bit read only mode R5 16bits for setting wait time The wait time should be in the range of some 100ns after switching the flash access mode for stabilization of the Flash ROM The wait function is a simple delay loop that needs a...

Page 1006: ...r updating an application the user bootloader causes the erase of flash sectors where the application is located Flash section where the Boot Security Vector is located and the section of the bootloader itself may not be erased After erasing the bootloader has to handle the programming of the application If during this procedure problems like reset or power down occur the program ming can be start...

Page 1007: ...der 2 have to be called to erase the sector where user bootloader 1 and the Magic Number are located After erasing program the new user bootloader to the section As last step the Magic Number should be set to 0x000A897A This procedure guarantees that there is started always a valid bootloader If after erasing or during programming user bootloader 1 a reset or a power down occurs user bootloader 2 ...

Page 1008: ...992 Chapter 53 Fixed Mode Reset Vector BOOT ROM 5 Bootloader Update Strategy ...

Page 1009: ... programs in word 32 bit length units Flash writing is not possible Actual Flash Memory access is performed in d word 64 bit length units 2 32 bit CPU mode CPU reads writes and executes programs in word 32 bit length units Actual Flash Memory access is performed in word 32 bit length units 3 16 bit CPU mode CPU reads and writes in half word 16 bit length units Program exectuion from the Flash is n...

Page 1010: ...LASH interface Control signal Address Data Interface with FLASH writer when in FLASH mode CPU CPU core A0 to A20 DQ0 to DQ31 DQ0 to DQ31 A0 to A20 32 bit 32 bit 16 bit FLASH memory Control signal A0 to A17 DQ0 to DQ15 Control signal Control signal A0 to A17 Address DQ0 to DQ15 Data CPU FLASH interface Control signal Address Data Interface with FLASH writer when in FLASH mode CPU CPU core A0 to A20...

Page 1011: ...1088kB 16x64kB 8x8kB as used on MB91F467DA SA0 SA2 SA4 SA6 14 0000h addr 14 FFFFh addr 2 0 FA addr addr 00 4000h addr 00 4000h 2 addr 2 4 addr 4 05 0000h SA1 SA3 SA5 SA7 14 0000h addr 14 FFFFh addr 2 1 FA addr addr 00 4000h addr 00 4000h 2 addr 2 4 addr 4 04 E000h SA8 SA10 SA12 SA14 SA16 SA18 SA20 SA22 04 0000h addr 13 FFFFh addr 2 0 FA addr addr 02 0000h addr 02 0000h 2 addr 2 4 addr 4 0C 0000h S...

Page 1012: ...d in Flash memory while the Flash is being written erased Specifying the mode Use the Flash setting procedure located in the Boot ROM at address 0000 BF60H with R4 2 bits set to 00B to set this mode Refer to Chapter 53 Fixed Mode Reset Vector BOOT ROM Page No 983 Flash memory always goes to 32 bit mode after a reset is cleared when the CPU is running Description of operation When reading or execut...

Page 1013: ...s are expected in CPU registers R4 and R5 R4 2bits LSB of register for setting the flash access mode b 00 32bit read write mode b 01 16bit read write mode b 1x 64bit read only mode R5 16bits for setting wait time The wait time should be in the range of some 100ns after switching the flash access mode for stabilization of the Flash ROM The wait function is a simple delay loop that needs about 3 CPU...

Page 1014: ... pins by directly linking some of the signals to the Flash memory unit s control signal In this mode the Flash memory appears to the external pins as a stand alone unit This mode is generally set when writing erasing using the parallel Flash programmer In this mode all operations of the Flash memory s Auto Algorithms are available For correspondence between the MCU pins and Flash memory s interfac...

Page 1015: ...s Write cycle 3rd Bus Write cycle 4th Bus Read write cycle 5th Bus Write cycle 6th Bus Write cycle Address Data Address Data Address Data Address Data Address Data Address Data Read reset 1 XXXXH F0H Read Reset 4 x557H AAH yAAFH 55H x557H F0H RA RD Writing 4 x557H AAH yAAFH 55H x557H A0H PA PD Chip erase 6 x557H AAH yAAFH 55H x557H 80H x557H AAH yAAFH 55H x557H 10H Sector erase 6 x557H AAH yAAFH 5...

Page 1016: ...ernally and validates the margins of written cells Auto write operation ends when the bit 7 data matches the data written to this bit via data polling see 3 Hardware sequence flag Flash memory then returns to read mode and no longer accepts write addresses As a result at this time Flash memory requests the next valid address Thus data polling indicates that writing is ongoing During writing all co...

Page 1017: ...e the last sector erase command was written sector erase begins In other words to erase multiple sectors simultaneously each sector must be entered within 50us of the other after which commands may no longer be accepted It is possible to monitor whether successive sector erase commands are valid via bit 3 see 3 Hardware sequence flag After finishing Flash memory returns to read mode Other commands...

Page 1018: ... suspend read mode the user can write to the Flash memory by writing a write command sequence This mode is called erase suspend write mode In this mode data writes to sectors where erase has not been paused are enabled but for other sectors it is the same as normal byte writing While in erase suspend write mode when data is read sequentially from an erase suspended sector bit 2 is toggled This mod...

Page 1019: ... more information Value 0 read from RDY bit Flash memory is currently writing or erasing At this time write and erase commands are not accepted Value 1 read from RDY bit Flash memory is currently on standby for read write or erase Table 7 2 List of Hardware Sequence Flag States Status DPOLL Bit 7 TOGGLE Bit 6 TLOVER Bit 5 SETIMR Bit 3 TOGGL2 Bit 2 Executing Auto write Inverted data Toggles 0 0 1 W...

Page 1020: ...ive reads are performed while the auto write or erase algorithm is executing the Flash memory outputs the result of toggling between 1 and 0 to bit 6 After the auto write or erase algorithm terminates bit 6 stops toggling in response to successive reads and outputs valid data The toggle bit becomes effective after the final write cycle of the command sequence in question Note that when writing if ...

Page 1021: ... accepted If a read is performed while in sector erase suspend mode the Flash memory outputs 1 if the address indicated by the address signal belongs to an erased sector If it does not belong to an erased sector bit 3 of the value read from the address indicated by the address signal is output bit 2 Toggle bit 2 TOGGL2 During sector erase This toggle bit is used in addition to the bit 6 toggle bit...

Page 1022: ...ing Function Figure 7 5 Write erase Determination Sequence Using Toggle bit Function VA write address Erased sector address during sector erase Non protected sector address during chip erase Since D7 changes at the same time as D5 even if D5 1 D7 must be rechecked Start write erase Read D0 to D7 address VA Read D0 to D7 address VA D7 Data Write erase Fail D5 1 D7 Data Write erase Pass YES YES YES ...

Page 1023: ...via parallel Flash programmer This Flash memory allows writing via an external device by means of the parallel Flash programmer In this state pin functions equivalent to the stand alone product MBM29LV400TC are assigned to the device s external pins and operation of the CPU halts In Flash memory mode the address line connections are changed from CPU mode to mapping within the memory area See the s...

Page 1024: ...1008 Chapter 54 Flash Memory 8 Caution ...

Page 1025: ...read protection for all flash sectors depending on device mode Individual write protection for each flash sector depending on device mode Write protection level depending on device mode Security vector re fetch sequence for security status update after chip erase CRC checksum calculation CRC32 AAL5 algorithm CRC polygon is x 32 x 26 x 23 x 22 x 16 x 12 x 11 x 10 x 8 x 7 x 5 x 4 x 2 x 1 ...

Page 1026: ...16 The setting of the Flash Security Vector FSV1 bits 31 16 is responsible for the read and write protection modes Explanation of the bits in the Flash Security Vector FSV1 31 16 FSV1 31 19 FSV1 18 Write Protection Level FSV1 17 Write Protection FSV1 16 Read Protection Flash Security Mode set all to 0 set to 0 set to 0 set to 1 Read Protection all device modes except INTVEC mode MD 2 0 000 set all...

Page 1027: ...and the data width configuration of the embedded flash memory Therefore always check the appropriate datasheet if the data shown here are valid for the product you are using See Chapter 54 Flash Memory Page No 993 for an overview about the sector organisation of the Flash Memory FSV1 bit Sector Enable Write Protection Disable Write Protection Comment FSV1 0 SA0 set to 0 set to 1 FSV1 1 SA1 set to ...

Page 1028: ...set to 0 set to 1 FSV2 3 SA11 set to 0 set to 1 FSV2 4 SA12 set to 0 set to 1 FSV2 5 SA13 set to 0 set to 1 FSV2 6 SA14 set to 0 set to 1 FSV2 7 SA15 set to 0 set to 1 FSV2 8 SA16 set to 0 set to 1 FSV2 9 SA17 set to 0 set to 1 FSV2 10 SA18 set to 0 set to 1 FSV2 11 SA19 set to 0 set to 1 FSV2 12 SA20 set to 0 set to 1 FSV2 13 SA21 set to 0 set to 1 FSV2 14 SA22 set to 0 set to 1 FSV2 15 SA23 set ...

Page 1029: ...checksum sequence cannot be started even if 0FH is written 31 30 29 28 27 26 25 24 bit CRC31 S7 CRC30 S6 CRC29 S5 CRC28 S4 CRC27 S3 CRC26 S2 CRC25 S1 CRC24 S0 1 1 1 1 1 1 1 1 Initial value INIT pin input watchdog reset X X X X X X X X Initial value Software reset R W R W R W R W R W R W R W R W Attribute 23 22 21 20 19 18 17 16 bit CRC23 CRC22 CRC21 CRC20 CRC19 CRC18 CRC17 CRC16 1 1 1 1 1 1 1 1 In...

Page 1030: ... AAL5 algorithm with the polygon x 32 x 26 x 23 x 22 x 16 x 12 x 11 x 10 x 8 x 7 x 5 x 4 x 2 x 1 FSCR1 Address 7104h Access Byte read Word write See Meaning of Bit Attribute Symbols Page No 10 for details of the attributes CRC31 CRC0 Function CRC32 Checksum read only 31 30 29 28 27 26 25 24 bit RDY 0 0 0 0 0 0 0 0 Initial value INIT pin input watchdog reset X X X X X X X X Initial value Software r...

Page 1031: ...ss The CSZ3 0 setting is first translated into a mask value CRC32 Startaddress CSA 15 0 12 0x000 CRC32 Endaddress CSA 15 0 or MASK 12 0xFFF RDY Function 0 CRC32 sequence running or not yet started 1 CRC32 sequence ready data in the FSCR0 register is valid CSZ3 0 Function 0000 CRC32 sequence size mask is 4 kByte 0001 CRC32 sequence size mask is 8 kByte 0010 CRC32 sequence size mask is 16 kByte 0011...

Page 1032: ...1016 Chapter 55 Flash Security 4 Register ...

Page 1033: ...1017 Chapter 56 Electrical Specification Chapter 56 Electrical Specification See the appropriate data sheet for the electrical specification of each device ...

Page 1034: ...1018 Chapter 56 Electrical Specification ...

Page 1035: ...FR60 MB91460 Series Hardware Manual European Microcontroller Design Centre Author MBo ...

Page 1036: ......

Page 1037: ... FUJITSU SEMICONDUCTOR CONTROLLER MANUAL FR60 32 BIT MICROCONTROLLER MB91460 Series User s Manual Jan 2005 the zero edition Published FUJITSU LIMITED Electronic Devices Edited European Microcontroller Design Centre ...

Page 1038: ......

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