549
Chapter 31 External Bus
4.Endian and Bus Access
Figure 4-13 Example of Connecting the MB91460 Series to External Devices
4.2 Little Endian Bus Access
Little endian (LER) external bus access is performed for an area for which the little endian meth-
od is set.
Little endian bus access on the MB91460 series is implemented by using the bus access oper-
ation used for the big endian method. Basically, the order of output addresses and control signal
output are the same as for the big endian method and the byte locations on the data bus are
swapped in accordance with the bus width.
Note that, when a connection is made, the big endian area and the little endian area must be
kept physically separate.
■
Differences between Little Endian and Big Endian
The following explains the differences between little endian and big endian.
The order of addresses that are output is the same for little endian and big endian.
The data bus control signal used for 32/16/8-bit bus width is the same for little endian and big endian.
●
Word access
The byte data on the MSB side for big endian address 00 becomes byte data on the LSB side when the little
endian method is used.
For a word address, the locations of all four bytes in the word are reversed:
00 -> 11, 01 -> 10, 10 -> 01, 11 -> 00
D31
D07
D00
D00
D15
D00
D16 D15
D08 D07
D08 D07
D24 D23
This LSI
D31
to
D24
D23
to
D16
D15
to
D08
D07
to
D00
00
01
10
11
0
1
0
* For 16/8-bit devices, use the data bus on
the MSB side of this LSI.
32-bit device
(low-order 2 bits of
the address 00 to 11)
*16-bit device
(low-order 1 bit of
the address 0/1)
*8-bit device
WR0
WR1
WR2
WR3
Summary of Contents for FR Family FR60 Lite
Page 2: ...FUJITSU LIMITED ...
Page 3: ...FR60 32 BIT MICROCONTROLLER MB91460 Series User s Manual ...
Page 15: ...xi ...
Page 16: ...xii ...
Page 38: ...22 Chapter 2 MB91460 Rev A Rev B Overview 4 Block Diagram ...
Page 128: ...112 Chapter 4 CPU Architecture 9 Addressing ...
Page 153: ...137 Chapter 8 Device State Transition 3 State Transition Diagram ...
Page 154: ...138 Chapter 8 Device State Transition 3 State Transition Diagram ...
Page 169: ...153 Chapter 9 Reset 10 Caution ...
Page 170: ...154 Chapter 9 Reset 10 Caution ...
Page 180: ...164 Chapter 10 Standby 7 Q A ...
Page 182: ...166 Chapter 10 Standby 8 Caution ...
Page 199: ...183 Chapter 12 Instruction Cache 2 Main body structure Figure 2 3 I Cache Address Map ...
Page 200: ...184 Chapter 12 Instruction Cache 2 Main body structure Figure 2 4 I Cacheable Area ...
Page 222: ...206 Chapter 13 Clock Control 8 Caution ...
Page 232: ...216 Chapter 14 PLL Interface 7 Caution ...
Page 236: ...220 Chapter 15 CAN Clock Prescaler 3 Registers ...
Page 288: ...272 Chapter 19 Timebase Timer 8 Caution ...
Page 314: ...298 Chapter 22 Main Oscillation Stabilisation Timer 8 Caution ...
Page 326: ...310 Chapter 23 Sub Oscillation Stabilisation Timer 8 Caution ...
Page 348: ...332 Chapter 25 External Interrupt 8 Caution ...
Page 398: ...382 Chapter 26 DMA Controller 6 DMA External Interface ...
Page 402: ...386 Chapter 27 Delayed Interrupt 8 Caution ...
Page 412: ...396 Chapter 28 Bit Search 8 Caution ...
Page 521: ...505 Chapter 30 I O Ports 3 Port Register Settings ...
Page 522: ...506 Chapter 30 I O Ports 3 Port Register Settings ...
Page 574: ...558 Chapter 31 External Bus 4 Endian and Bus Access Byte Access ...
Page 628: ...612 Chapter 31 External Bus 13 Notes on Using the External Bus Interface ...
Page 706: ...690 Chapter 33 I2C Controller 4 Programming Flow Charts ...
Page 748: ...732 Chapter 34 CAN Controller 4 CAN Application ...
Page 762: ...746 Chapter 35 Free Run Timer 8 Caution ...
Page 790: ...774 Chapter 37 Output Compare 8 Caution ...
Page 838: ...822 Chapter 39 Programmable Pulse Generator 8 Caution ...
Page 850: ...834 Chapter 40 Pulse Frequency Modulator 4 PFM Operation and Setting ...
Page 886: ...870 Chapter 42 Sound Generator 3 Registers ...
Page 900: ...884 Chapter 43 Stepper Motor Controller 4 Caution ...
Page 939: ...923 Chapter 47 LCD Controller 3 Configuration Figure 3 2 Register List ...
Page 943: ...927 Chapter 47 LCD Controller 4 Registers Correspondence between VRAM and Common Segment Pins ...
Page 964: ...948 Chapter 48 Clock Monitor 8 Caution ...
Page 994: ...978 Chapter 51 Low Voltage Reset Interrupt 3 Registers ...
Page 998: ...982 Chapter 52 Regulator Control 3 Registers ...
Page 1008: ...992 Chapter 53 Fixed Mode Reset Vector BOOT ROM 5 Bootloader Update Strategy ...
Page 1024: ...1008 Chapter 54 Flash Memory 8 Caution ...
Page 1032: ...1016 Chapter 55 Flash Security 4 Register ...
Page 1034: ...1018 Chapter 56 Electrical Specification ...
Page 1035: ...FR60 MB91460 Series Hardware Manual European Microcontroller Design Centre Author MBo ...
Page 1036: ......
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