Chapter 10 XGATE (S12XGATEV3)
MC9S12XE-Family Reference Manual , Rev. 1.19
Freescale Semiconductor
455
Operation
RS – 0
⇒
NONE (translates to SUB R0, RS, R0)
Subtracts zero from the content of register RS using binary subtraction and discards the result.
CCR Effects
Code and CPU Cycles
TST
Test Register
TST
N
Z
V
C
∆
∆
∆
∆
N:
Set if bit 15 of the result is set; cleared otherwise.
Z:
Set if the result is $0000; cleared otherwise.
V:
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RS[15] & result[15]
C:
Set if there is a carry from the bit 15 of the result; cleared otherwise.
RS1[15] & result[15]
Source Form
Address
Mode
Machine Code
Cycles
TST RS
TRI
0
0
0
1
1
0
0
0
RS1
0
0
0
0
0
P
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages