Chapter 15 Inter-Integrated Circuit (IICV3) Block Description
MC9S12XE-Family Reference Manual , Rev. 1.19
Freescale Semiconductor
581
The number of clocks from the falling edge of SCL to the first tap (Tap[1]) is defined by the values shown
in the scl2tap column of
, all subsequent tap points are separated by 2
IBC5-3
as shown in the
tap2tap column in
. The SCL Tap is used to generated the SCL period and the SDA Tap is used
to determine the delay from the falling edge of SCL to SDA changing, the SDA hold time.
IBC7–6 defines the multiplier factor MUL. The values of MUL are shown in the
.
Table 15-5. Prescale Divider Encoding
IBC5-3
(bin)
scl2start
(clocks)
scl2stop
(clocks)
scl2tap
(clocks)
tap2tap
(clocks)
000
2
7
4
1
001
2
7
4
2
010
2
9
6
4
011
6
9
6
8
100
14
17
14
16
101
30
33
30
32
110
62
65
62
64
111
126
129
126
128
Table 15-6. Multiplier Factor
IBC7-6
MUL
00
01
01
02
10
04
11
RESERVED
SCL Divider
SDA Hold
SCL
SDA
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