Freescale Semiconductor HCS12X, Reference Manual

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Appendix A Electrical Characteristics
MC9S12XE-Family Reference Manual , Rev. 1.19
1250 Freescale Semiconductor
- External cycle time (selected
by EXSTR) t
cyce
- 60
∞
80
∞
- 120
∞
160
∞
ns
1 External cycle time
(EXSTR+1EWAIT) t
cycew
- 80
∞
100
∞
- 160
∞
200
∞
ns
2 Address
1
valid to RE fall t
ADRE
D 4 - 4 - D 13 - 13 - ns
3 Pulse width, RE
2
PW
RE
D 68 - 88 - D 138 - 178 - ns
4 Address valid to WE fall t
ADWE
D 4 - 4 - D 15 - 15 - ns
5 Pulse width, WE PW
WE
D 58 - 78 - D 118 - 158 - ns
6 Read data setup time
(if ITHRS = 0) t
DSR
D 19 - 19 - D 38 - 38 - ns
Read data setup time
(if ITHRS = 1) t
DSR
D 23 - 23 - D N/A ns
7 Read data hold time t
DHR
D 0 - 0 - D 0 - 0 - ns
8 Read enable access time t
ACCR
D 49 - 69 - D 65 - 105 - ns
9 Write data valid to WE fall t
WDWE
D 5 - 5 - D 5 - 5 - ns
10 Write data setup time t
DSW
D 63 - 93 - D 123 - 163 - ns
11 Write data hold time t
DHW
D 6 - 6 - D 4 - 4 - ns
12 Address to EWAIT fall t
ADWF
D 0 16 0 36 D 0 20 0 - ns
13 Address to EWAIT rise t
ADWR
D 30 39 50 58 D 50 61 90 101 ns
1
Includes the following signals: ADDRx, UDS, LDS, and CSx.
2
Affected by EWAIT.
Table A-31. Example 1b: Normal Expanded Mode Timing at 50MHz bus (EWAIT enabled)
No. Characteristic Symbol
V
DD5
= 5.0V V
DD5
= 3.3V
Unit
C
2 stretch
cycles
3 stretch
cycles
C
2 stretch
cycles
3 stretch
cycles
Min Max Min Max Min Max Min Max
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages