Freescale Semiconductor HCS12X, Reference Manual

Page: 495 / 1326

Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
MC9S12XE-Family Reference Manual , Rev. 1.19
Freescale Semiconductor 495
S12XECRG performs a quality check on the incoming clock signal. As soon as clock quality check
indicates a valid Oscillator Clock signal the reset sequence starts using the Oscillator clock. If after 50
check windows the clock quality check indicated a non-valid Oscillator Clock the reset sequence starts
using Self-Clock Mode.
Figure 11-22 and Figure 11-23 show the power-up sequence for cases when the RESET pin is tied to V
DD
and when the RESET pin is held low.
Figure 11-22. RESET Pin Tied to V
DD
(by a Pull-up Resistor)
Figure 11-23. RESET Pin Held Low Externally
11.6 Interrupts
The interrupts/reset vectors requested by the S12XECRG are listed in Table 11-18 . Refer to MCU
specification for related vector addresses and priorities.
Table 11-18. S12XECRG Interrupt Vectors
Interrupt Source
CCR
Mask
Local Enable
Real time interrupt I bit CRGINT (RTIE)
LOCK interrupt I bit CRGINT (LOCKIE)
SCM interrupt I bit CRGINT (SCMIE)
RESET
Internal POR
128 SYSCLK
64 SYSCLK
Internal RESET
Clock Quality Check
(no Self-Clock Mode)
) (
) (
) (
Clock Quality Check
RESET
Internal POR
Internal RESET
128 SYSCLK
64 SYSCLK
(no Self Clock Mode)
) (
) (
) (
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages