Freescale Semiconductor HCS12X, Reference Manual

Page: 169 / 1326

Chapter 2 Port Integration Module (S12XEP100PIMV1)
MC9S12XE-Family Reference Manual , Rev. 1.19
Freescale Semiconductor 169
Table 2-88. PTL Register Field Descriptions
Field Description
7
PTL
Port L general purpose input/output data —Data Register
Port L pin 7 is associated with the TXD signal of the SCI7 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
6
PTL
Port L general purpose input/output data —Data Register
Port L pin 6 is associated with the RXD signal of the SCI7 module .
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
5
PTL
Port L general purpose input/output data —Data Register
Port L pin 5 is associated with the TXD signal of the SCI6 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
4
PTL
Port L general purpose input/output data —Data Register
Port L pin 4 is associated with the RXD signal of the SCI6 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
3
PTL
Port L general purpose input/output data —Data Register
Port L pin 3 is associated with the TXD signal of the SC5 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
2
PTL
Port L general purpose input/output data —Data Register
Port L pin 2 is associated with the RXD signal of the SCI5 module .
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
1
PTL
Port L general purpose input/output data —Data Register
Port L pin 3 is associated with the TXD signal of the SCI4 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
0
PTL
Port L general purpose input/output data —Data Register
Port L pin 2 is associated with the RXD signal of the SCI4 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages