Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)
MC9S12XE-Family Reference Manual , Rev. 1.19
604
Freescale Semiconductor
SOF: Start of Frame
CPU bus: CPU related read/write data bus
CAN bus: CAN protocol related serial bus
oscillator clock: Direct clock from external oscillator
bus clock: CPU bus realated clock
CAN clock: CAN protocol related clock
16.1.2
Block Diagram
Figure 16-1. MSCAN Block Diagram
16.1.3
Features
The basic features of the MSCAN are as follows:
•
Implementation of the CAN protocol — Version 2.0A/B
— Standard and extended data frames
— Zero to eight bytes data length
— Programmable bit rate up to 1 Mbps
1
— Support for remote frames
•
Five receive buffers with FIFO storage scheme
•
Three transmit buffers with internal prioritization using a “local priority” concept
•
Flexible maskable identifier filter supports two full-size (32-bit) extended identifier filters, or four
16-bit filters, or eight 8-bit filters
1. Depending on the actual bit timing and the clock jitter of the PLL.
RXCAN
TXCAN
Receive/
Transmit
Engine
Message
Filtering
and
Buffering
Control
and
Status
Wake-Up Interrupt Req.
Errors Interrupt Req.
Receive Interrupt Req.
Transmit Interrupt Req.
CANCLK
Bus Clock
Configuration
Oscillator Clock
MUX
Presc.
Tq Clk
MSCAN
Low Pass Filter
Wake-Up
Registers
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
