Operating Principles
Laser 1000/1500 Service Manual
2.2.1.3 Interrupt Control
The
standard cell determines the
priority
of the interrupt and outputs it to terminals
-
Then an interrupt is sent to the CPU. If the CPU
accepts the interrupt, terminals
-
all go HIGH to indicate the interrupt acceptance to the
standard cell. The
standard
confirms that
-
are HIGH (interrupt acknowledge), and then sets
the VPA terminal to LOW and informs the CPU that this is automatic vector interrupt. This
initializes the interrupt process. The
standard cell has a controller for the automatic vector
interrupt.
2.2.1.4
DRAM Management
The video controller uses DRAMs for the system RAM and for the V-RAM.
In the
1000, a standard
x DRAM is mounted
providing a total of
sockets
32, 33, 34, 10, 11, 12, 13, 17, 16, 15, 14 are optional
DRAM sockets. These sockets can use
x
4-bit DRAMs or
x 4-bit
In the EPL-5200/ActionLaser 1500, a standard
x
16-bit DRAM and four
x 4-bit DRAMs
are mounted in locations
31,32,33,34, which provide a total of
The sockets IC1O, 11,
12, 13, 17, 16, 15, 14 are optional DRAM sockets. These sockets can use
x 4-bit DRAMs or
x 4-bit DRAMs.
The DRAMs (including optional chips) are managed by the
and
standard cells.
The
standard cell handles the main management. The
outputs
WE, and
OE signals. The
DRAM is controlled directly by the
Other DRAMs (including
optional chips) are controlled by the CAS, WE, and OE signals from the
and also controlled
bv the
from the E05A84. The
the
output
to
DRAM size
4-bit DRAM or256K x4-bit DRAM).
-
REFRSH
RASEN
I
Address
W E D a t a
RASO
,
3rd Block
I
T
T
ICI 1
2nd
Block
I
IC32
I
I
, IC34
I
Block
Figure 2-40. DRAM Management
