5 Implementation of EtherNet/IP
5.3 VSC-Vendor Specific Classes
116
XI/ON: XNE-GWBR-2ETH-IP
09/2011 MN05002007Z-EN
www.eaton.com
120
(78h)
TX count
G/S
USINT
This value is transferred together with every
data segment.
The TX count values are sequential:
00->01->10->11->00…
(decimal: 0->1->2->3->0…)
Errors in this sequence show the loss of
data segments.
121
(79h)
RX count
acknowledge
G/S
USINT
This value is a copy of RX count.
RX count has been transmitted together
with the last data segment of the process
input data.
RX count acknowledge is an acknowledge
for the successful transmission of the data
segment with RX count.
122
(7Ah)
Status reset
control
G/S
BOOL
STATRES:
This bit is set to reset the STAT bit in the
process input data.
With the change from 1 to 0 the status bit is
reset
(from 0 to 1).
If this bit is 0, all changes in TRANSMIT
BYTE count, TRANSMIT count and
RECEIVE count acknowledge are ignored.
Flushing the transmit-/ receive-buffer with
Process control data (Attr. 123)
is possible.
If this bit is 1 or with the change from 0 to 1,
the flushing of the transmit-/ receive-buffer
with Process control data (Attr. 123)
is not possible.
123
(7Bh)
Process control
data
G/S
BYTE
Bit 0 = transmit-buffer flush,
Bit 1 = receive-buffer flush
124
(7Ch)
TX data
G/S
ARRAY OF
BYTE
Defines the transmit-data (0...7)
125
(7Dh)
TX data and
release
S
ARRAY OF
BYTE
Defines the data to be transmitted via
RS232 (0...7) + transmission is released/
charged immediately
126
(7Eh)
reserved
Table 56:
Object instance
Attr.
no.
dec.
(hex.)
Attribute name
G
et/
S
et
Type
Description
