8 BIOS Setup
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PT-E731, PT-E731S, PT-E731H, PT-E731HS User’s Manual
Description Choices
CAS Latency Time
When synchronous DRAM is installed, the number of clock
cycles of CAS latency depends on the DRAM timing. Do not
reset this field from the default value specified by the
system designer.
DRAM RAS# to CAS# delay
This field lets you insert a timing delay between the CAS
and RAS strobe signals, used when DRAM is written to,
read from, or refreshed. Fast gives faster performance; and
Slow gives more stable performance. This field applies only
when synchronous DRAM is installed in the system.
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM
at F0000h-FFFFFh, resulting in better system performance.
However, if any program writes to this memory area, a
system error may result.
