PCI Configuration Registers
BCM5718 Programmer’s Guide
Broadcom
®
January 29, 2016 • 5718-PG108-R
Page 283
DMA Read/Write Control Register (Offset: 0x6C)
Interrupt Check
11
RW
0
Set this bit to enable the interrupt check
RCB Check
10
RW
0
Set this bit to enable RCB check
Enable Tagged Status Mode
9
RW
0
When set, an unique 8-bit tag value will be
inserted into the Status block status tag
Mask Interrupt Mode
8
RW
0
When set, the interrupt is masked. However, the
internal interrupt state (host coalescing event)
will not be cleared
Enable indirect access
7
RW
0
Set this bit to enable indirect addressing mode
Enable Register Word Swap
6
RW
0
Set this bit to enable word swapping when
accessing registers through the PCI target
device
Enable Clock Control register
read/write capability
5
RW
0
Set this bit enable clock control register read/
write capability, otherwise, the clock control
register is read only
Enable PCI State register read/
write capability
4
RW
0
Set this bit to enable PCI state register read/write
capability, otherwise the register is read only
Enable Endian Word Swap
3
RW
0
Set this bit to enable endian word swapping
when accessing through PCIE target interface
Enable Endian Byte Swap
2
RW
0
Set this bit to enable endian byte swapping when
accessing through PCIE target interface.
Note:
Setting register 0x68 bit 2 (Enable Endian
Byte Swap) causes PCI configuration reads to
the following registers to become swapped:
• 0x40
• 0x68 – 0x9C
• 0xF4 – 0xFF
This is different behavior from previous
NetXtreme controllers. Reference BCM5718
Family errata relating to byte swap control for
additional information.
Mask Interrupt
1
RW
0
Setting this bit will mask future interrupt events
from being generated. Setting this bit will not
clear or deassert the internal interrupt state, nor
will it deassert the external interrupt state.
Clear Interrupt
0
WO
0
Setting this bit will clear interrupt as long as the
mask interrupt bit is not set. If mask interrupt bit
is set, then writing 1 to this bit will not deassert
interrupt, however, it will clear the internal
unmasked interrupt state, so if the interrupt is
later unmasked, the interrupt will deassert.
Name
Bits
Access
Default
Value
Description
Reserved
31:29
RW
0x0
–
Name
Bits
Access
Default
Value
Description