BECKWITH ELECTRIC M?3311A, Instruction Book

Page: 373 / 450

A–40
M‑3311A Instruction Book
System Setpoints and Settings (Cont.'d)
IPSlogic
#1
o
Disable
o
Enable
Initiating Outputs:
o
#1
o
#2
o
#3
o
#4
o
#5
o
#6
o
#7
o
#8
o
#9
o
#10
o
#11
o
#12
o
#13
o
#14
o
#15
o
#16
Initiating Outputs Logic Gate:
o
OR
o
AND
Initiating 87H/TPhase:
o
A
o
B
o
C
Initiating Function Trip:
o
24DT#1
o
24DT #2
o
24IT
o
27 #1
o
27 #2
o
27 #3
o
46DT‑W2
o
46IT‑W2
o
46DT‑W3
o
46IT‑W3
o
49
o
50 #1
o
50 #2
o
50 #3
o
50 #4
o
50 #5
o
50 #6
o
50BF‑W1
o
50BF‑W2
o
50BF‑W3
o
50G‑W2 #1
o
50G‑W2 #2
o
50G‑W3 #1
o
50G‑W3 #2
o
50N#1
o
50N#2
o
50N#3
o
50N#4
o
50N#5
o
50N#6
o
51#1
o
51#2
o
51#3
o
51G‑W2
o
51G‑W3
o
51N#1
o
51N#2
o
51N#3
o
59#1
o
59#2
o
59#3
o
59G#1
o
59G#2
o
59G#3
o
81#1
o
81#2
o
81#3
o
81#4
o
87H
o
87T
o
87GD‑W2 #1
o
87GD‑W2 #2
o
87GD‑W3 #1
o
87GD‑W3 #2
o
TF
o
TCM
o
IPSlogic #2
o
IPSlogic #3
o
IPSlogic #4
o
IPSlogic #5
o
IPSlogic #6
o
BM‑W1
o
BM‑W2
o
BM‑W3
Initiating 87H/T Phase Logic Gate:
o
OR
o
AND
Initiating 87H/T Phase Logic Gate:
o
‑‑‑
o
NOT
Initiating Inputs:
o
#1
o
#2
o
#3
o
#4
o
#5
o
#6
o
#7
o
#8
o
#9
o
#10
o
#11
o
#12
o
#13
o
#14
o
#15
o
#16
o
#17
o
#18
Initiating Inputs Logic Gate:
o
OR
o
AND
Initiate via Communication Point:
o
Blocking Inputs:
o
#1
o
#2
o
#3
o
#4
o
#5
o
#6
o
#7
o
#8
o
#9
o
#10
o
#11
o
#12
o
#13
o
#14
o
#15
o
#16
o
#17
o
#18
Initiating Inputs Logic Gate:
o
OR
o
AND
Initiating Inputs Logic Gate:
o
None
o
NOT
Block via Communication Point:
o
Initiating Outputs/Inputs/Function Trip/87H‑T Logic Gate:
o
OR
o
AND
Delay: _____ 1 – 65500 (Cycles)
Reset/Dropout Delay: _____ 0 – 65500 (Cycles)
o
Reset
o
Dropout
Outputs:
o
#1
o
#2
o
#3
o
#4
o
#5
o
#6
o
#7
o
#8
o
#9
o
#10
o
#11
o
#12
o
#13
o
#14
o
#15
o
#16
Reset Latched Outputs
o
Profile Switch:
o
#1
o
#2
o
#3
o
#4
o
Not Activated
Figure A‑4 System Setpoints and Settings (page 30 of 39)