Areva MiCOM P441, Technical Manual

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P44x/EN HW/E33 Relay Description
Page 8/44 MiCOM P441/P442 & P444
2. HARDWARE MODULES
The relay is based on a modular hardware design where each module performs a separate
function within the relay operation. This section describes the functional operation of the
various hardware modules.
2.1 Processor board
The relay is based around a TMS320C32 floating point, 32-bit digital signal processor (DSP)
operating at a clock frequency of 20MHz. This processor performs all of the calculations for
the relay, including the protection functions, control of the data communication and user
interfaces including the operation of the LCD, keypad and LEDs.
The processor board is located directly behind the relay’s front panel which allows the LCD
and LEDs to be mounted on the processor board along with the front panel communication
ports. These comprise the 9-pin D-connector for RS232 serial communications (e.g. using
MiCOM S1 and Courier communications) and the 25-pin D-connector relay test port for
parallel communication. All serial communication is handled using a two-channel 85C30
serial communications controller (SCC).
The memory provided on the main processor board is split into two categories, volatile and
non-volatile: the volatile memory is fast access (zero wait state) SRAM which is used for the
storage and execution of the processor software, and data storage as required during the
processor’s calculations. The non-volatile memory is sub-divided into 3 groups: 2MB of flash
memory for non-volatile storage of software code and text together with default settings,
256kB of battery backed-up SRAM for the storage of disturbance, event, fault and
maintenance record data and 32kB of E2PROM memory for the storage of configuration
data, including the present setting values.
2.2 Co-processor board
A second processor board is used in the relay for the processing of the current differential
protection algorithms. The processor used on the second board is the same as that used on
the main processor board. The second processor board has provision for fast access (zero
wait state) SRAM for use with both program and data memory storage. This memory can be
accessed by the main processor board via the parallel bus, and this route is used at power-
on to download the software for the second processor from the flash memory on the main
processor board. Further communication between the two processor boards is achieved via
interrupts and the shared SRAM. The serial bus carrying the sample data is also connected
to the co-processor board, using the processor’s built-in serial port, as on the main processor
board.
The co-processor board also handles all communication with the remote differential relay(s).
This is achieved via optical fibre communications and hence the co-processor board holds
the optical modules to transmit and receive data over the fibre links.
From software version B1.0, coprocessor board woks at 150Mhz.
2.3 Internal communication buses
The relay has two internal buses for the communication of data between different modules.
The main bus is a parallel link which is part of a 64-way ribbon cable. The ribbon cable
carries the data and address bus signals in addition to control signals and all power supply
lines. Operation of the bus is driven by the main processor board which operates as a
master while all other modules within the relay are slaves.
The second bus is a serial link which is used exclusively for communicating the digital
sample values from the input module to the main processor board. The DSP processor has a
built-in serial port which is used to read the sample data from the serial bus. The serial bus is
also carried on the 64-way ribbon cable.