Unified Fieldbus Controller UFC100-L2 – Basic mode operation
Page 11
Rev. 1.0
Proprietary and confidential information of Aniotek Inc.
21 May 2018
Table 10: UFC Interrupt mask register
Interrupt mask
Bit no.
Name
7
ERS
6
RTI
5
TED
4
RED
3
TFI
2
RFI
1
LCD
0
Not used
2.2.10
Error mask
Address:
0x07
Reset value:
0xFB
This register controls error interrupts specified in Error status register in the same order of error reasons. When a field of this
register is set to ‘1’, then the corresponding error in Error status register is masked (does not affect the ERS bit in the
Interrupt status register). When the CPU needs to receive any error interrupt, corresponding fields of this register should be
cleared to ‘0’ prior to waiting for the error interrupt.
Table 11: UFC Error mask register
Error mask
Bit no.
Name
7
FFER
6
JI
5
TLM
4
CNS
3
FCSE
2
Not used
1
RFR
0
NEPT
2.2.11
Transmit frame length
Address:
0x08, 0x09
Reset value:
0x0000
This 10-bit register stores the length of the frame as number of bytes to be transferred from memory to the Transmit FIFO.
This count does not include Preamble, Start Delimiter and End Delimiter. The FCS is not included in this count, unless
transmission of FCS is disabled by TFCS. It is necessary to write a non-zero value to this register before transferring data to
the Transmit FIFO.
This register decrements by one when the CPU writes one byte into Transmit FIFO. If the CPU tries to write more bytes than
the value of Transmit length register then the extra bytes are not written to the Transmit FIFO. If the CPU does so after
TRON has been set to ‘1’, then the transmission is aborted and ‘TLM’ is set to ‘1’. If the CPU does so before TRON has
been set to ‘1’, then the transmission is aborted when the CPU tries to set TRON to ‘1’ and ‘TLM’ is set to ‘1’ at that time.
The CPU can read and write this register. When the CPU reads the lower byte of this register, the current value of the register
is not latched. If a transmission is active, then the reading of this register may not return correct value. The address 0x08
accesses the lower 8-bits of the frame length. The upper 6-bits at address 0x09 are read as zeros.
