Unified Fieldbus Controller UFC100-L2 – Basic mode operation
Page 15
Rev. 1.0
Proprietary and confidential information of Aniotek Inc.
21 May 2018
The counting frequency of this register depends upon the setting of ‘NDE’ in Clock mode register - 2.2.15.
2.2.18
GAP time
Address:
0x14
Reset value
0xFF
This register stores the time to guarantee minimum gap between successive frames on the bus. It is used only when
transmitting a frame. The internal GAP timer starts whenever the bus becomes inactive and stops when it becomes equal to
the value set in GAP time register. When transmission is started by setting TRON bit of Control register, the transmission is
started only if the internal GAP timer has stopped. The unit of this register depends upon the setting of ‘GPE’ in Clock mode
register - 2.2.15. The CPU can read back this register. The internal GAP timer itself cannot be read.
2.2.19
Watch time
Address:
0x16, 0x17
Reset value
0xFFFF
These registers hold threshold to detect “no activity” on the bus. UFC100-L2 has an internal Watch-time counter that is a
monotonously increasing counter and is reset by detecting Start Delimiter or End Delimiter in the RxS signal. When the
content of Watch-time counter reaches the value set in Watch time register and if RTI is not masked, RTI interrupt status is
set to ‘1’. The Watch-time counter is reset whenever the bus is active. This counter is also reset by setting CT bit of Timer
control register (see 2.2.21). The unit of this register is eight (8) bit time.
The address 0x16 accesses the lower 8-bits of the Watch time threshold.
The CPU can read back these registers. The internal Watch-time counter itself cannot be read.
2.2.20
Token counter
Address:
0x18, 0x19
Reset value
0x0000
These registers are used to read the value from or write the value to the internal Token-time counter. The internal counter is a
16-bit down counter. It is reset to zero at the start of UFC100-L2 operation. Whenever it has non-zero value, it counts down
once every byte time – transmission duration of one byte. It stops count down at zero value.
The content of the internal Token-time counter is latched to these registers when LTR bit of Timer control register (see
2.2.21) is set.
The content of these registers are loaded to the internal Token-time counter when any data is written to higher byte register
($19). This implies lower byte ($18) should be written first. It is also loaded from the received PT frame.
2.2.21
Timer control
Address:
0x1A
Reset value
0x00
This write-only register is used to control various internal timers and counters. Read of this register returns 0x00.
Table 16: UFC Timer control register
Timer control
Bit no.
Name
7
Not used
6
LTN
5
LTR
4 – 2
Not used
1
CT
0
Not used
LTN
Latch Node-timer
Writing ‘1’ to this field snaps the value of the internal Node-time counter into Node-time register – address 0x12, 0x13.
