Aniotek UFC100-L2, User Manual

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Unified Fieldbus Controller UFC100-L2 – Basic mode operation Page 12
Rev. 1.0 Proprietary and confidential information of Aniotek Inc. 21 May 2018
2.2.12 FIFO control Register
Address: 0x0B
Reset value: 0x00
Table 12: UFC FIFO control register
FIFO control
Bit no. Name
7 Not used
6 CRF
5, 4 RCTRL
3 Not used
2 CTF
1, 0 TCTRL
CRF Clear Receive FIFO
Writing ‘1’ to this field clears the Receive FIFO, its error status and the FIFO becomes empty. This field is
automatically reset to ‘0’ by the UFC100-L2.
RCTRL Receive FIFO threshold
The value of this field sets the FIFO threshold that is used to set RFI field – see 2.2.7.
RCTRL Threshold
00
8 bytes,
01 16 bytes,
10 24 bytes,
11 32 bytes.
CTF Clear Transmit FIFO
Writing ‘1’ to this field clears the Transmit FIFO, its error status and the FIFO becomes empty. It also resets Transmit
length register to zero. This field is automatically reset to ‘0’ by the UFC100-L2.
TCTRL Transmit FIFO threshold
The value of this field sets the FIFO threshold that is used to set TFI field – see 2.2.7. The threshold value depends upon
TRON.
RCTRL Threshold
TRON = ‘0’ TRON = ‘1’
00 4 bytes, 8 bytes,
01 8 bytes, 16 bytes,
10 16 bytes, 32 bytes,
11 24 bytes, 64 bytes.
Some of the software programs try to fill the Transmit FIFO before turning on the transmission by setting TRON to ‘1’.
The FIFO threshold is lower during this time, so that there is less delay in turning on the transmission.