Unified Fieldbus Controller UFC100-L2 – Basic mode operation
Page 1
Rev. 1.0
Proprietary and confidential information of Aniotek Inc.
21 May 2018
1 I
NTRODUCTION
The UFC100-L2 (Unified Fieldbus Controller) is a peripheral that that can be used in a Fieldbus Device or Host to provide a
complete solution for implementing Fieldbus equipment. The UFC100-L2 includes all of time-critical functions in the
hardware. It implements part of Physical and Data Link Layers for the Foundation Fieldbus H1 and Profibus-PA. This
document describes the mode of operation that is compatible with existing Fieldbus controllers. It shows the pin signals, the
internal registers that can be accessed by a software program, electrical specifications and package dimensions. It also
includes procedures for software device drivers and hardware test.
1.1
Overview
Figure 1: UFC100-L2 Block Diagram
1.2
Features
It is:
·
Compliant to IEC 61158-2 Physical layer at 31.25 Kbit/s,
·
Compliant to IEC 61158-4 Data Link layer,
·
RoHS certified 44 pin LQFP package,
·
Operating voltage 2.7 to 3.6 V,
·
Low current consumption suitable for Field devices,
·
Flexible 8-bit CPU bus interface suitable for all types of processors,
·
128 byte Transmit and Receive FIFO to reduce the number of the interrupts to the CPU.
CPU Bus
Interface
Interrupt Encoder
Jabber Control and Data Link Timers
(Bus Inactivity, GAP, Token, Node Time)
MAU
Interface
Clock
Generator
Data Link State Machine
Clock
Synchronizer
Serial to
Parallel
FCS
Checker
Manchester
Decoder
Delimiter
Detector
FC
Decoder
FIFO
(128)
Data Link Address Filter
Receive
Machine
Control
Receive Machine
INTn
11
CSn
4
RDn
2
WRn
3
RDY
27
RQ
25
D7-D0
36-29
RSTn
7
ATYP
38
CTYP
37
A6, A5
9, 8
FIFO
(128)
Parallel
to Serial
FCS
Generator
Manchester
Encoder
Delimiter
Generator
Transmit
Machine
Control
Transmit Machine
TxS
19
TxEn
20
RxS
21
RxA
22
RES1
13
RES2
14
TxRn
16
CLKIN
N
5
12
RES0
FLT1n
24
FLT0n
26
Shade indicates
Enhanced
Functions
A4-A0
1, 44-41
TxA
15
