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Unified Fieldbus Controller UFC100-L2 – Basic mode operation

Page 31

Rev. 1.0

Proprietary and confidential information of Aniotek Inc.

21 May 2018

4.4.2

Freescale Type CPU

Figure 13: Freescale Bus Read Cycle Timing Diagram

Figure 14: Freescale Bus Write Cycle Timing Diagram

ADRS

CSn

RWn

DACKn

t15

DATA

t10

t12

t13

RDY

t5b

t14

t11

DSn or ASn

t5c

t5a

ADRS

CSn

DACKn

DATA

t8a

t10

t12

t13

RDY

t5b

t11

RWn

DSn or ASn

t5c

t5a

Summary of Contents for UFC100-L2

Page 1: ...Aniotek Inc UNIFIED FIELDBUS CONTROLLER UFC100 L2 BASIC MODE USER S MANUAL...

Page 2: ...not meant for military space medical or life sustaining equipment Aniotek Inc does not make any warranty of fitness or suitability of this product for any purpose Aniotek Inc reserves the right to ma...

Page 3: ...t status 8 2 2 8 Error status 9 2 2 9 Interrupt mask 10 2 2 10 Error mask 11 2 2 11 Transmit frame length 11 2 2 12 FIFO control Register 12 2 2 13 FIFO status 13 2 2 14 FIFO data 13 2 2 15 Clock mode...

Page 4: ...2 4 5 MAU INTERFACE TIMINGS 33 4 5 1 MAU Interface Timings 33 4 6 OTHER TIMINGS 34 4 6 1 Reset Timings 34 4 6 2 Interrupt Timings 34 1 PACKAGE FEHLER TEXTMARKE NICHT DEFINIERT 2 TEST PROCEDURES 37 2 1...

Page 5: ...atures It is Compliant to IEC 61158 2 Physical layer at 31 25 Kbit s Compliant to IEC 61158 4 Data Link layer RoHS certified 44 pin LQFP package Operating voltage 2 7 to 3 6 V Low current consumption...

Page 6: ...0 L2 The UFC100 L2 has function package and pins same as UFC100 L1 except in L2 the following pins are not 5 V tolerant Pin Signal 7 RESETn 21 RxS 22 RxA 26 FLT0n 37 CTYP 38 ATYP The UFC100 L2 draws l...

Page 7: ...7 Vdd P Power plus side 18 Vss P Power negative side 19 TxS O L Transmit signal to medium attachment unit 20 TxEn O H Transmit control to medium attachment unit 21 RxS ICH Receive Signal from medium a...

Page 8: ...ted only after the entire frame has been stored in this memory The CPU can cancel the current reception The current reception is also cancelled if any error is detected but the Receive FIFO is not cle...

Page 9: ...IFO 0D DATA R W 0x00 Transmit Receive data to from FIFO 0E Reserved 1 Not used 0F Reserved 1 Not used 10 Clock mode R W 0x00 DL mode Timer enables 11 Timer status R 0x00 Node timer status 12 Node time...

Page 10: ...er the CPU writes any value to Mode register even if the value to be written is 0x00 so that the internal clock does not start at a higher than the desired frequency Table 4 UFC Mode register Mode Bit...

Page 11: ...mission the DMA transfer starts when TRON and DMA both are set to 1 The Transmit length register is decremented by 1 for every byte written to the Transmit FIFO The DMA transfer continues until either...

Page 12: ...asked interrupts are used to activate INTn hardware signal 2 2 6 Status Address 0x03 Reset value 0x82 or 0x83 Table 7 UFC Status register Status Bit no Name 7 ARDY 6 3 Not used 2 RFRY 1 TFRY 0 CD ARDY...

Page 13: ...control register see 2 2 12 The TFI status becomes 1 only if the last byte of the current transmission has not been read out of the FIFO TFI is reset to 0 when Transmitter has read all bytes of the fr...

Page 14: ...nd any of the following error is detected during the reception detection of N or N code which is not a part of Start or End Delimiter or End Delimiter is not on the byte boundary or RxA is negated bef...

Page 15: ...the frame as number of bytes to be transferred from memory to the Transmit FIFO This count does not include Preamble Start Delimiter and End Delimiter The FCS is not included in this count unless tran...

Page 16: ...field see 2 2 7 RCTRL Threshold 00 8 bytes 01 16 bytes 10 24 bytes 11 32 bytes CTF Clear Transmit FIFO Writing 1 to this field clears the Transmit FIFO its error status and the FIFO becomes empty It...

Page 17: ...whenever there is at least one byte in the FIFO TFOR Transmit FIFO overrun This field is set to 1 when the Transmit FIFO is full and the CPU or DMA tries to write another byte to Transmit FIFO This fi...

Page 18: ...bit is automatically cleared to 0 when this register is read NOTE Multiple overflows cannot be detected by this register 2 2 17 Node time Address 0x12 0x13 Reset value 0x0000 This is a holding registe...

Page 19: ...counter is reset whenever the bus is active This counter is also reset by setting CT bit of Timer control register see 2 2 21 The unit of this register is eight 8 bit time The address 0x16 accesses th...

Page 20: ...d confidential information of Aniotek Inc 21 May 2018 LTR Latch Token timer Writing 1 to this field snaps the value of the internal Token time counter into Token counter register address 0x18 0x19 CT...

Page 21: ...e RDY DACKn signal and if the CPU cannot insert enough wait states then it has to use software to poll a status bit ARDY inside UFC100 L2 This bit indicates that it is ready for next cycle 4 The input...

Page 22: ...t may become low at the start of the Read or Write cycle to indicate that the CPU has to wait It becomes high when the CPU can complete the cycle The Figure 2 shows interface to Renesas microcontrolle...

Page 23: ...use the non multiplexed bus as shown in the Figure 3 The INT0 input is used for DMA request UFC100 L1 A6 A5 A4 D7 D0 A0 9 8 1 41 36 29 CSn RDn WRn RDY INTn RQ CLKIN CTYP ATYP MS2 TxA TxS TxEn RxS RxA...

Page 24: ...r Write cycle to indicate to the CPU that it can complete the cycle It becomes high when the CPU completes the cycle The Figure 4 shows interface to such CPU This example is meant for new designs beca...

Page 25: ...the start of the Read or Write cycle to indicate that the CPU has to wait It becomes high when the CPU can complete the cycle The RDY output requires some amount of logic to convert it to DTACK signal...

Page 26: ...ite cycle to indicate to the CPU that it can complete the cycle It becomes high when the CPU completes the cycle 3 2 5 Power PC The PowerPC has a bus interface which is similar to Intel type CPU It ha...

Page 27: ...1 The TxA signal is always high during active transmission for all transmit modes It can be used to enable the transmit buffer in the MAU that drives voltage or to change the bias current in the MAU...

Page 28: ...external MAU should generate active RxA signal only after detecting sufficient activity beyond the noise threshold and for sufficient time so that noise above threshold can also be filtered After the...

Page 29: ...2 INTn This output becomes active when it needs to interrupt the CPU The active polarity is low This signal stays active as long as any one of the interrupt sources in the UFC100 L2 is active The rese...

Page 30: ...e 0 0 3 VDD V VIH Input high voltage ICH type 0 7 VDD VDD V VH Input hysteresis 0 4 V IL Input leakage current 5 A VOL Output low voltage IOL 0 1 mA 0 2 V VOL Output low Voltage RES0 RES1 RES2 IOL 8 m...

Page 31: ...8 and Figure 9 below It was measured while the device was continuously transmitting and receiving in full duplex using DMA with continuous Read and Write access to the device Figure 8 Typical operatin...

Page 32: ...Inc 21 May 2018 4 3 Clock Input Timings The timings are shown in the Table 21 and the Figure 10 Table 21 Clock Timings Name Description Min Max TCLK Clock input period VDD 2 7 to 3 6 V 125 ns 1000 ns...

Page 33: ...n it can issue successive access without delay If the CPU cannot use RDY DACKn signal and if the successive bus access cannot be delayed then the CPU has to check completion of the prior access by rea...

Page 34: ...DACKn to valid Data delay 20 3 t8b Positive edge of CLKIN to valid Data delay 30 3 t9 RDn negation to tristate Data invalid Data delay 3 15 t10 RDn WRn negation to DACKn negation delay 0 15 t11 RDn WR...

Page 35: ...ek Inc 21 May 2018 4 4 2 Freescale Type CPU Figure 13 Freescale Bus Read Cycle Timing Diagram Figure 14 Freescale Bus Write Cycle Timing Diagram ADRS CSn t2 t3 RWn DACKn t1 t15 DATA t10 t12 t13 RDY t5...

Page 36: ...t10 DSn negation to DACKn RDY negation delay 0 15 t11 DSn assertion duration 10 t12 DSn inactive time 10 t13 CSn inactive time 10 t14 Valid Data to WRn negation setup time 5 t15 WRn negation to inval...

Page 37: ...ut average period 30 s 34 s tRTR Receive signal input transition time 200 ns tRJTR Receive signal zero crossing jitter 2 s tLOCK Receive lock time 110 s 2 tRxAH Receive activity signal hold time 0 Not...

Page 38: ...voltage is below minimum value Figure 19 Reset Signal Timings 4 6 2 Interrupt Timings Table 27 Interrupt Timings Num Description Min Max Notes tTXINTD Active INTn output to end of transmission delay...

Page 39: ...ve FIFO becomes empty The last received byte is available for transfer at the start of end delimiter Therefore in DMA mode the FIFO is likely to become empty before the end delimiter is detected 3 If...

Page 40: ...M MAX MIN NOM MAX A 1 60 0 063 A1 0 05 0 15 0 002 0 006 A2 1 35 1 40 1 45 0 053 0 055 0 057 b 0 22 0 30 0 38 0 009 0 012 0 015 c 0 09 0 20 0 004 0 008 D 12 00 BSC 0 472 BSC E 12 00 BSC 0 472 BSC e 0 8...

Page 41: ...pts For hardware test use any threshold setting 5 Write to GAP time register 0x14 The value depends upon the Data Link layer configuration For test purpose set it to 0x10 8 bytes 6 Write to Watch time...

Page 42: ...1 then there was an error 8 If there was an error then first read FIFO status register 0x0C and then Error status register 0x05 to find the reason for the error Clear the FIFO status register by writi...

Page 43: ...en Error status register 0x05 to find the reason for the error Clear the FIFO status register by writing 1 to CRF and CTF in FIFO control register 0x0B 9 Compare the received data bytes with transmitt...

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