Unified Fieldbus Controller UFC100-L2 – Basic mode operation
Page 35
Rev. 1.0
Proprietary and confidential information of Aniotek Inc.
21 May 2018
2.
If end delimiter is not detected and RxA becomes inactive, then this delay is from the end of activity. If DMA is enabled,
then the interrupt becomes active only after the receive FIFO becomes empty. The last received byte is available for
transfer at the start of end delimiter. Therefore, in DMA mode, the FIFO is likely to become empty before the end
delimiter is detected.
3.
If DMA is enabled and the receive FIFO does not become empty until after the end delimiter is detected, then INTn
becomes active this delay after last RQ.
Figure 20: TED Interrupt Timings
Figure 21: RED Interrupt Timings
RxS
End Delimiter
RxA
t
RXINTD1
INTn
RQ
t
RXINTD2
INTn
RQ
TxS
INTn
End Delimiter
t
TXINTD
TxEn
Internal
TRON
