Aniotek UFC100-L2, User Manual

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Unified Fieldbus Controller UFC100-L2 – Basic mode operation Page 3
Rev. 1.0 Proprietary and confidential information of Aniotek Inc. 21 May 2018
Table 1: UFC100-L2 Pin out
Pin
no.
Name Type Reset
value Description
1 A4 ICH CPU Address bus
2 RDn/EDSn ICH Read Strobe (Intel mode), E or DSn (Freescale mode)
3 WRn/RWn ICH Write Strobe (Intel mode), RWn – Read or Write select (Freescale
mode)
4 CSn ICH Chip Select – active state enables Read or Write access.
5 CLKIN ICH Clock input – the frequency has to be one of 1, 2, 4 or 8 Mhz.
6 Vss P Power negative side
7 RESETn ICH Reset – active (low).
8 A5 ICH This pin can be connected to CPU address A5, or to Vdd or Vss.
9 A6 ICH This pin can be connected to CPU address A6, or to Vdd or Vss.
10 MS2 ICH Reserved for test use; connect it to Vss.
11 INTn O H Interrupt request to the CPU
12 RES0 O L Reserved
13 RES1 O L Reserved
14 RES2 O L Reserved
15 TxA O L It is used as TxA output, which is high while transmitter is active.
16 TxRn O H Low pulse of 8 µs duration whenever TxS changes.
17 Vdd P Power plus side
18 Vss P Power negative side
19 TxS O L Transmit signal to medium attachment unit
20 TxEn O H Transmit control to medium attachment unit
21 RxS ICH Receive Signal from medium attachment unit
22 RxA ICH Receive activity (carrier detect) from medium attachment unit
23 TST0 ICH Test input; connect to Vss in normal operation.
24 FLT1n ICH Not used – this pin can be connected either Vss or Vdd.
25 RQ O L DMA request output, one pulse per byte to be transferred
26 FLT0n ICH Not used – this pin can be connected either Vss or Vdd.
27 RDY
DACKn
O H
H ATYP high: low value indicates that the data is ready or accepted.
ATYP low: high value indicates that the data is ready or accepted.
28 Vss P Power negative side
29 D0 BCH TS CPU Data bus
30 D1 BCH TS CPU Data bus
31 D2 BCH TS CPU Data bus
32 D3 BCH TS CPU Data bus
33 D4 BCH TS CPU Data bus
34 D5 BCH TS CPU Data bus
35 D6 BCH TS CPU Data bus
36 D7 BCH TS CPU Data bus
37 CTYP ICH Type of CPU – Low: Intel, High: Freescale
38 ATYP ICH Type of bus access – Low: RDY output, High: DACKn output
39 Vdd P Power plus side
40 Vss P Power negative side
41 A0 ICH CPU Address bus
42 A1 ICH CPU Address bus
43 A2 ICH CPU Address bus
44 A3 ICH CPU Address bus