© 2011 Advanced Micro Devices, Inc.
46136 AMD RX881 Databook 1.40
Proprietary
7-1
Chapter 7
Testability
7.1
Test Capability Features
The RX881 has integrated test modes and capabilities. These test features cover both the ASIC and board level testing.
The ASIC tests provide a very high fault coverage and low DPM (Defect Per Million) ratio of the part. The board level
tests modes can be used for motherboard manufacturing and debug purposes. The following are the test modes of the
RX881:
•
Full scan implementation on the digital core logic that provides about 99% fault coverage through ATPG (Automatic
Test Pattern Generation Vectors).
•
Dedicated test logic for the on-chip custom memory macros to provide complete coverage on these modules.
•
Improved access to the analog modules and PLLs in the RX881 to allow full evaluation and characterization of these
modules.
•
A JTAG test mode (which is not entirely compliant to the IEEE 1149.1 standard) to allow board level testing of
neighboring devices.
•
An XOR TREE test mode on all the digital I/O’s to allow for proper soldering verification at the board level.
•
A VOH/VOL test mode on all digital I/O’s to allow for proper verification of output high and output low voltages at
the board level.
These test modes can be accessed through the settings on the instruction register of the JTAG circuitry.
7.2
Test Interface
7.3
XOR Test
7.3.1
Description of a Generic XOR Tree
An example of a generic XOR tree is shown in the
Figure 7-1
.
Table 7-1
Pins on the Test Interface
Pin Name
Ball number
Type
Description
TESTMODE
D13
I
IEEE 1149.1 test port reset
NC
B8
I
TMS: Test Mode Select (IEEE 1149.1 test mode select)
NC
A9
I
TDI: Test Mode Data In (IEEE 1149.1 data in)
NC
B9
I
TCLK: Test Mode Clock (IEEE 1149.1 clock)
NC
D9
O
TDO: Test Mode Data Out (IEEE 1149.1 data out)
POWERGOOD
A10
I
I/O Reset