CPU HyperTransport™ Interface
© 2011 Advanced Micro Devices, Inc.
46136 AMD RX881 Databook 1.40
Proprietary
3-5
3.3
CPU HyperTransport™ Interface
3.4
PCI Express
®
Interfaces
3.4.1
1 x 16 Lane Interface for External Graphics
3.4.2
A-Link Express II Interface for Southbridge
Note:
The widths of the A-Link Express II interface and the general purpose links for external devices are configured
through the programmable strap GPPSB_LINK_CONFIG, which is programmed through RX881’s registers. See the
RS880 ASIC Family Register Reference Guide
, order# 46142, and the
RS880 ASIC Family Register Programming
Requirements,
order# 46141, for details.
Table 3-1 CPU HyperTransport
™
Interface
Pin Name
Type
Power
Domain
Ground
Domain
Functional Description
HT_RXCAD[15:0]P,
HT_RXCAD[15:0]N
I
VDDHTRX
VSS
Receiver Command, Address, and Data Differential Pairs
HT_RXCLK[1:0]P,
HT_RXCLK[1:0]N
I
VDDHTRX
VSS
Receiver Clock Signal Differential Pairs. Forwarded clock signal. Each byte of
RXCAD uses a different clock signal. Data is transferred on each clock edge.
HT_RXCTL[1:0]P,
HT_RXCTL[1:0]N
I
VDDHTRX
VSS
Receiver Control Differential Pairs. For distinguishing control packets from
data packets.
HT_TXCAD[15:0]P,
HT_TXCAD[15:0]N
O
VDDHTTX
VSS
Transmitter Command, Address, and Data Differential Pairs
HT_TXCLK[1:0]P,
HT_TXCLK[1:0]N
O
VDDHTTX
VSS
Transmitter Clock Signal Differential Pairs. Each byte of TXCAD uses a
different clock signal. Data is transferred on each clock edge.
HT_TXCTL[1:0]P,
HT_TXCTL[1:0]N
O
VDDHTTX
VSS
Transmitter Control Differential Pairs. Forwarded clock signal. For
distinguishing control packets from data packets.
HT_RXCALN
Other
VDDHTRX
VSS
Receiver Calibration Resistor to VDD_HT power rail.
HT_RXCALP
Other
VDDHTRX
VSS
Receiver Calibration Resistor to Ground
HT_TXCALP
Other
VDDHTTX
VSS
Transmitter Calibration Resistor to HTTX_CALN
HT_TXCALN
Other
VDDHTTX
VSS
Transmitter Calibration Resistor to HTTX_CALP
Table 3-2 1 x 16 Lane PCI Express
®
Interface for External Graphics
Pin Name
Type
Power
Domain
Ground
Domain
Integrated
Termination
Functional Description
GFX_TX[15:0]P,
GFX_TX[15:0]N
O
VDDPCIE
VSSAPCIE
50
between
complements
Transmit Data Differential Pairs. Connect to external connector for
an external graphics card on the motherboard (if implemented).
GFX_RX[15:0]P,
GFX_RX[15:0]N
I
VDDPCIE
VSSAPCIE
50
between
complements
Receive Data Differential Pairs. Connect to external connector for an
external graphics card on the motherboard (if implemented).
Table 3-3 1 x 4 Lane A-Link Express II Interface for Southbridge
Pin Name
Type
Power
Domain
Ground
Domain
Integrated
Termination
Functional Description
SB_TX[3:0]P,
SB_TX[3:0]N
O
VDDPCIE
VSSAPCIE
50
between
complements
Transmit Data Differential Pairs. Connect to the corresponding
Receive Data Differential pairs on the Southbridge.
SB_RX[3:0]P,
SB_RX[3:0]N
I
VDDPCIE
VSSAPCIE
50
between
complements
Receive Data Differential Pairs. Connect to the corresponding
Transmit Data Differential pairs on the Southbridge.