46136 AMD RX881 Databook 1.40
© 2011 Advanced Micro Devices, Inc.
1-2
Proprietary
RX881 Features
•
Supports x1, x2, x4, x8, x12 and x16 polarity inversion.
1.2.3 A-Link Express II Interface
•
One x4 A-Link Express II interface for connection to an AMD Southbridge. The A-Link Express II is a proprietary
interface developed by AMD basing on the PCI Express technology, with additional Northbridge-Southbridge
messaging functionalities.
•
Supports programmable lane reversal to ease motherboard layout.
1.2.4 System Clocks
•
Support for an external clock chip to generate PCIe and A-Link Express II clocks. Alternatively, internal generation
for these clocks, with clock input from an SB800-series Southbridge, can be used (subject to characterization with
actual RX881 and SB800-series devices).
1.2.5 Power Management Features
•
Single chip solution in 55nm, 1.1V CMOS technology.
•
Full ACPI 2.0 and IAPC (Instantly Available PC) power management support.
•
The Chip Power Management Support logic supports four device power states defined for the OnNow Architecture—
On, Standby, Suspend, and Off. Each power state can be achieved by software control bits.
•
Hardware controlled intelligent clock gating enables clocks only to active functional blocks, and is completely
transparent to software.
•
Support for Cool'n'Quiet™ via FID/VID change.
•
Support for AMD PowerNow!™.
•
Clocks to every major functional block are controlled by a unique dynamic clock switching technique that is
completely transparent to the software. By turning off the clock to the block that is idle or not used at that point, the
power consumption can be significantly reduced during normal operation.
•
Supports dynamic lane reduction for the PCIe graphics interface when coupled with an AMD-based graphics device,
adjusting lane width according to required bandwidth.
1.2.6 PC Design Guide Compliance
The RX881 complies with all relevant Windows Logo Program (WLP) requirements from Microsoft for WHQL
certification.
1.2.7 Test Capability Features
The RX881 has a variety of test modes and capabilities that provide a very high fault coverage and low DPM (Defect Per
Million) ratio:
•
Full scan implementation on the digital core logic through ATPG (Automatic Test Pattern Generation Vectors).
•
Dedicated test logic for the on-chip custom memory macros to provide complete coverage on these modules.
Table 1-1 Possible Configurations for the PCIe
®
General Purpose Links
Config. B
Config. C
Config. C2
Config. E
Config. K
Config. L
GPP1
x4
x4
x2
x2
x2
x1
GPP2
-
-
-
-
-
x1
GPP3
-
-
x2
x1
x2
x1
GPP4
-
-
-
x1
-
x1
GPP5
x2
x1
x2
x1
x1
x1
GPP6
-
x1
-
x1
x1
x1