© 2011 Advanced Micro Devices, Inc.
46136 AMD RX881 Databook 1.40
Proprietary
2-1
Chapter 2
Functional Descriptions
This chapter describes the functional operation of the major interfaces of the RX881 system logic.
Figure 2-1, “RX881
Internal Block Diagram,”
illustrates the RX881 internal blocks and interfaces.
Figure 2-1 RX881 Internal Block Diagram
2.1
Host Interface
The RX881 is optimized to interface with AMD processors through the HyperTransport
TM
interface. This section presents
an overview of the HyperTransport
interface. For a detailed description of the interface, please refer to the
HyperTransport I/O Link Specification
from the HyperTransport Consortium.
Figure 2-2, “Host Interface Block
Diagram,”
illustrates the basic blocks of the host bus interface of the RX881.
CP
U
Int
e
rf
ac
e
Register Interface
Root
IO Con
tro
ller
AMD CPU
Graphics
Controller
Complex
A-Li
nk-E II
PCI
e
®
In
ter
fa
c
e
GP
P In
ter
fac
e
PC
Ie
®
Expansion
Slots or
On-board
Devices
G
fx
In
ter
fac
e
(6
x 1
Lan
es)
(1
x
4 L
anes)
(1
x 16 Lan
es)
Southbridge
HyperTransport™
Unit