46136 AMD RX881 Databook 1.40
© 2011 Advanced Micro Devices, Inc.
3-6
Proprietary
Clock Interface
3.4.3
6 x 1 Lane Interface for General Purpose External Devices
Note:
The widths of the A-Link Express II interface and the general purpose links for external devices are configured
through the programmable strap GPPSB_LINK_CONFIG, which is programmed through RX881’s registers. See the
RS880 ASIC Family Register Reference Guide
, order# 46412, and the
RS880 ASIC Family Register Programming
Requirements,
order# 46141, for details.
3.4.4
Miscellaneous PCI Express
®
Signals
3.5
Clock Interface
Table 3-4 6 x 1 Lane PCI Express
®
Interface for General Purpose External Devices
Pin Name
Type
Power
Domain
Ground
Domain
Integrated
Termination
Functional Description
GPP_TX[5:0]P,
GPP_TX[5:0]N
O
VDDPCIE
VSSAPCIE
50
between
complements
Transmit Data Differential Pairs. Connect to external connectors on
the motherboard for add-in card or ExpressCard support.
GPP_RX[5:0]P,
GPP_RX[5:0]N
I
VDDPCIE
VSSAPCIE
50
between
complements
Receive Data Differential Pairs. Connect to external connectors on
the motherboard for add-in card or ExpressCard support.
Table 3-5 PCI Express
®
Interface for Miscellaneous PCI Express
®
Signals
Pin Name
Type
Power
Domain
Ground
Domain
Functional Description
PCE_CALRN
Other
VDDPCIE
VSSAPCIE
RX Impedance Calibration. Connect to VDDPCIE on the motherboard with an
external resistor of an appropriate value.
PCE_CALRP
Other
VDDPCIE
VSSAPCIE
TX Impedance Calibration. Connect to GND on the motherboard with an external
resistor of an appropriate value.
Table 3-6 Clock Interface
Pin Name
Type
Power
Domain
Ground
Domain
Integrated
Termination
Functional Description
HT_REFCLKP,
HT_REFCLKN
I
VDDA18H
TPLL
VSSAHT
–
HyperTransport™ 100MHz reference clock differential pair
External clock mode:
Input from external clock source, as a
reference clock for the HyperTransport interface.
Internal clock mode*:
Input from the SB8xx Southbridge, as a
reference clock for the HyperTransport interface.
GFX_REFCLKP,
GFX_REFCLKN
I/O
VDDPCIE VSSAPCIE
50
between
complements
Clock Differential Pair for external graphics.
External clock mode:
Input from the external clock generator, as a
reference clock for external graphics.
Internal clock mode*:
Not used. Pull down following instructions in
the
RS880-Series IGP Motherboard Schematic Review
Checklist.
GPPSB_REFCLKP,
GPPSB_REFCLKN
I
VDDPCIE VSSAPCIE
50
between
complements
Clock Differential Pair for Southbridge and general purpose PCIe
®
devices.
External clock mode:
Input from the external clock generator, as a
reference clock for A-Link Express II and general purpose PCIe.
Internal clock mode*:
Input from the SB8xx Southbridge, as a
reference clock for A-Link II and general purpose PCIe.
GPP_REFCLKP,
GPP_REFCLKN
O
VDDPCIE VSSAPCIE
50
between
complements
Clock Differential Pair for general purpose PCIe devices.
External clock mode:
Not used. Can be left unconnected, or
connected to the external clock generator for maintaining system
compatibility with the RX881.
Internal clock mode*:
Output to a GPP device slot as a GPP clock.
REFCLK_P,
REFCLK_N
I
VDD33
VSS
–
Do not connect.
*Note:
Internal clock mode is only available when using an SB8xx Southbridge. Use of the internal clock generator function is subject to
characterization with actual RX881 and SB8xx devices