Power Management Pins
© 2011 Advanced Micro Devices, Inc.
46136 AMD RX881 Databook 1.40
Proprietary
3-7
3.6
Power Management Pins
3.7
Miscellaneous Pins
Table 3-7 Power Management Pins
Pin Name
Type
Power
Domain
Ground
Domain
Functional Description
LDTSTOP#
I
VDD33
VSS
HyperTransport™ Stop. Used for systems requiring power management. It is a
single-ended signal for input from the Southbridge to enable and disable the
HyperTransport link during system state transitions.
Note:
For platforms supporting DDR2 system memory, 1.8V signalling can be
used on the signal. For platforms supporting DDR3 system memory, follow
recommendations in the
RS880-Series IGP Motherboard Schematic Review
Checklist.
ALLOW_LDTSTOP
OD
VDD33
VSS
Allow LDTSTOP. The signal is used for controlling LDTSTOP assertions. It is an
output to the SB.
1 = LDTSTOP# can be asserted
0 = LDTSTOP# has to be de-asserted
Note:
For platforms supporting DDR2 system memory, 1.8V signalling can be
used on the signal. For platforms supporting DDR3 system memory, follow
recommendations in the
RS880-Series IGP Motherboard Schematic Review
Checklist.
SYSRESET#
I
VDD33
VSS
Global Hardware Reset. This signal comes from the Southbridge.
POWERGOOD
I
VDD18
VSS
Input from the motherboard signifying that the power to the RX881 is up and ready.
Signal High means all power planes are valid. It is not observed internally until it
has been high for more than six consecutive REFCLK cycles. The rising edge of
this signal is deglitched.
Table 3-8 Miscellaneous Pins
Pin Name
Type
Power
Domain
Ground
Domain
Integrated
Termination
Functional Description
DAC_HSYNC
Other
VDD33
VSS
50k
programmable:
PU/PD/none
This is a strap pin for a reserved strap function. See
Table 3-11,
“Strap Definitions for the RX881,”
for details.
DAC_VSYNC
Other
VDD33
VSS
50k
programmable:
PU/PD/none
This is a strap pin for the STRAP_DEBUG_BUS_GPIO _ENABLE#
strap function. See
Table 3-11, “Strap Definitions for the
RX881,”
for details.
GPIO[4:2]
I/O
VDDR3
VSS
50k
programmable:
PU/PD/none
General Purpose I/O. These pins can also be used as outputs to
the voltage regulator for pulse-width modulation of various voltages
on the motherboard.
MEM_VREF
Other
–
VSS
None
Connect the pin to ground
NC
–
–
–
–
No connect. These pins should be left unconnected to anything.
STRP_DATA
I/O
VDD33
VSS
50k
programmable:
PU/PD/none
I
2
C interface data signal for external EEPROM based strap loading.
Can also be used as GPIO, or as output to the voltage regulator for
pulse-width modulation of RX881’s core voltage.
SUS_STAT#
Other
VDD33
VSS
50k
programmable:
PU/PD/none
This is a strap pin for the LOAD_EEPROM_STRAPS# strap
function. See
Table 3-11, “Strap Definitions for the
RX881,”
for details.
TESTMODE
I
VDD33
VSS
–
When High, puts the RX881 in test mode and disables the RX881
from operating normally.