46136 AMD RX881 Databook 1.40
© 2011 Advanced Micro Devices, Inc.
4-2
Proprietary
PCI Express® Differential Clock AC Specifications
4.3
PCI Express
®
Differential Clock AC Specifications
4.4
Power Rail Power-up Sequence
Figure 4-1 RX881 Power Rail Power-up Sequence
Table 4-2 PCI Express
®
Differential Clock (GFX_REFCLK, GPPSB_REFCLK, 100MHz) AC Characteristics
Symbol
Description
Minimum
Maximum
Unit
Rising Edge Rate
Rising Edge Rate
0.6
4.0
V/ns
Falling Edge Rate
Falling Edge Rate
0.6
4.0
V/ns
T
PERIOD AVG
Average Clock Period Aquaria
-300
+2800
ppm
T
PERIOD ABS
Absolute Period (including jitter and spread spectrum
modulation)
9.847
10.203
ns
T
CCJITTER
Cycle to Cycle Jitter
-
150
Ps
Duty Cycle
Duty Cycle
40
60
%
Rise-Fall Matching
Rising edge rate () to falling edge rate
(REFCLK-) matching
-
20
%
Table 4-3 RX881 Power Rail Power-up Sequence
Symbol
Parameter
Voltage Difference During Ramping
Minimum (V)
Maximum (V)
T11
3.3-V rail ramps high relative to 1.8-V PLL and IO
transform rails
0
2.1
T12
1.8-V PLL and IO transform rails ramp high relative
to 1.1-V rail (PLLVDD, IOPLLVDD)
0
No restrictions
T13
1.1-V rail (PLLVDD, IOPLLVDD) ramps high relative
to VDDC (1.1V)
0
No restrictions
T11
T12
T13
3.3V Rail
(AVDD, VDD33)
1.8V PLL and IO
Transform Rail
(PLLVDD18, IOPLLVDD18, VDDA18HTPLL,
VDDA18PCIEPLL, AVDDDI, AVDDQ, VDD18)
1.1V Rail
(PLLVDD, IOPLLVDD)
1.1V VDDC
Note: There are no specific requirements for the following 1.1V or 1.2V rails: VDDHT, VDDHTRX, VDDHTTX, VDDPCIE