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6–10

Chapter 6: PHY IP Core for PCI Express (PIPE)

Interfaces

Altera Transceiver PHY IP Core

March 2012

Altera Corporation

User Guide

PIPE Interface

Table 6–8

 describes the signals in the PIPE interface.

Table 6–8. PIPE Interface (Part 1 of 2)

Signal Name

Direction

Description

pll_ref_clk

Sink

This is the 100 MHz input reference clock source for the PHY PLL. You can 
optionally provide a 125 MHz input reference clock by setting the 

PLL 

r

efe

r

ence clock f

r

equency

 parameter to 125 MHz as described in 

Table 6–3 on page 6–2

.

If you have enabled Configuration via Protocol (CvP) and your design 
includes other transceiver PHYs connected to the same Transceiver 
Reconfiguration Controller, then you should connect 

pll_ref_clk

 to the 

phy_mgmt_clk_clk

 signal of the Transceiver Reconfiguration Controller 

and the other transceiver PHYs. In addition, if your design includes more 
than one Transceiver Reconfiguration Controller on the same side of the 
FPGA, they all must share the 

phy_mgmt_clk_clk

 signal.

fixedclk

Sink

A 125 MHz clock used for the receiver detect circuitry. You must connect a 
125 MHz input clock signal for the fixedclk port. This clock can be derived 
from 

pll_ref_clk

.

pipe_txdetectrx_loopback

Sink

This signal instructs the PHY to start a receive detection operation. After 
power-up asserting this signal starts a loopback operation. Refer to section 
6.4 of the 

Intel PHY Interface for PCI Express (PIPE) Architecture

 

for 

a timing diagram. 

pipe_txelecidle

Sink

This signal forces the transmit output to electrical idle. Refer to section 7.3 
of the 

Intel PHY Interface for PCI Express (PIPE) Architecture

 

for 

timing diagrams. 

pipe_txdeemph

Sink

Transmit de-emphasis selection. In PCI Express Gen2 (5 Gbps) mode it 
selects the transmitter de-emphasis: 

■

1'b0: -6 dB

■

1'b1: -3.5 dB

pipe_txcompliance

Sink

When asserted for one cycle, sets the 8B/10B encoder output running 
disparity to negative. Used when transmitting the compliance pattern. Refer 
to section 6.11 of the 

Intel PHY Interface for PCI Express (PIPE) 

Architecture

 for more information. 

pipe_txmargin

Sink

Transmit V

OD

 margin selection. The PCI Express MegaCore

®

 function hard 

IP sets the value for this signal based on the value from the Link Control 2 
Register. This is 3 bits in the PIPE Specification.

pipe_rate

Sink

Specifies the link frequency, as follows:

■

0 –Gen1 operation, or 2.5 Gbps

■

1–Gen2 operation, or 5.0 Gbps

Figure 6–3 on page 6–12

 illustrates the timing of a rate switch from Gen1 

to Gen2 and back to Gen1.

Summary of Contents for PHY IP Core

Page 1: ... www altera com UG 01080 1 6 User Guide Altera Transceiver PHY IP Core Document last updated for Altera Complete Design Suite version Document publication date 11 1 SP2 March 2012 Feedback Subscribe Altera Transceiver PHY IP Core User Guide ...

Page 2: ...nductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advis...

Page 3: ... 3 4 Parameter Settings 3 4 General Options 3 4 Analog Options 3 5 Stratix IV Devices 3 5 Stratix V Devices 3 6 Interfaces 3 11 Ports 3 11 SDR XGMII TX Interface 3 12 SDR XGMII RX Interface 3 13 Status Interface 3 14 Clocks Reset and Powerdown 3 14 Serial Interface 3 17 Register Interface 3 17 Register Descriptions 3 18 Dynamic Reconfiguration 3 20 Dynamic Reconfiguration for Stratix IV Devices 3 ...

Page 4: ...V Devices 4 24 Simulation Files and Example Testbench 4 24 Chapter 5 Interlaken PHY IP Core Device Family Support 5 2 Parameter Settings 5 2 General Options 5 2 Advanced Options 5 3 Analog Settings 5 4 Interfaces 5 8 Ports 5 8 Avalon ST TX Interface 5 9 Avalon ST RX Interface 5 10 PLL Interface 5 12 TX and RX Serial Interface 5 12 Optional Clocks for Deskew 5 12 Registers 5 13 Register Description...

Page 5: ...Signals Optional 7 18 Reset Control and Status Optional 7 19 Register Interface 7 20 Register Descriptions 7 21 Dynamic Reconfiguration 7 23 Simulation Files and Example Testbench 7 24 Chapter 8 Low Latency PHY IP Core Device Family Support 8 1 Performance and Resource Utilization 8 2 Parameter Settings 8 3 General Options 8 3 Additional Options 8 5 PLL Reconfiguration Options 8 6 Analog Options 8...

Page 6: ...es 10 7 MIF Reconfiguration Management Avalon MM Master Interface 10 7 Transceiver Reconfiguration Interface 10 8 Reconfiguration Interface Management Interface 10 8 Reconfiguration Controller Memory Map 10 9 Transceiver Calibration Functions 10 10 Offset Cancellation 10 10 Duty Cycle Calibration 10 10 Auxiliary Transmit ATX PLL Calibration 10 10 PMA Analog Controls 10 11 EyeQ 10 12 DFE 10 14 AEQ ...

Page 7: ... PLLs In Multiple Transceiver PHY Instances 10 38 Loopback Modes 10 39 Chapter 11 Migrating from Stratix IV to Stratix V Devices Dynamic Reconfiguration of Transceivers 11 2 Dynamic Reconfiguration for Stratix V Transceivers 11 2 Dynamic Reconfiguration for Stratix IV Transceivers 11 2 XAUI PHY 11 3 Parameter Differences 11 3 Port Differences 11 4 PHY IP Core for PCI Express PHY PIPE 11 6 Paramete...

Page 8: ...viii Contents Altera Transceiver PHY IP Core March 2012 Altera Corporation User Guide ...

Page 9: ... the MAC for data transfer The control and status registers store device dependent information about the PCS and PMA modules You can access this device dependent information using the device independent Avalon MM interface reducing overall complexity of your design and the number of device dependent signals that you must expose in your top level module f For more information about the Avalon MM an...

Page 10: ...tions are 8B 10B 64B 66B or 64B 67B encoding and decoding rate matching and clock compensation scrambling and de scrambling word alignment phase compensation error monitoring and gearbox Figure 1 1 Altera Modular PHY Design To MAC To Embedded Controller To HSSI Pins Stratix V Device Transceiver PHY PMA PCS Customized functionality as required for 10GBase R XAUI Interlaken PCI Express PIPE Custom L...

Page 11: ...odate different reset requirements for different transceivers in your design instantiate multiple instances of a PHY IP core For example if your design includes 20 channels of the Custom PHY IP core with 12 channels running a custom protocol using the automatic reset controller and 8 channels requiring manual control of RX reset instantiate 2 instances of the Custom PHY IP core and customize one t...

Page 12: ...t order for reading these files into your simulation tool modelsim_example_script tcl this is an example file for compilation and simulation of the transceiver PHY IP core instance_name _sim cadence Simulation files for Cadence simulation tools instance_name _sim mentor Simulation files for Mentor simulation tools instance_name _sim synopsys Simulation files for Synopsys simulation tools Table 1 2...

Page 13: ...ted so that they can be used with the top level VHDL wrapper without using a mixed language simulator f For more information about simulating with ModelSim refer to the Mentor Graphics ModelSim Support chapter in volume 3 of the Quartus II Handbook 1 The transceiver PHY IP cores do not support the NativeLink feature in the Quartus II software Unsupported Features The protocol specific PHYs are not...

Page 14: ...1 6 Chapter 1 Introduction Unsupported Features Altera Transceiver PHY IP Core March 2012 Altera Corporation User Guide ...

Page 15: ...ww altera com Figure 2 1 shows the directory structure after you install an Altera IP core where path is the installation directory The default installation directory on Windows is C altera version number on Linux it is opt altera version number You can evaluate an IP core in simulation and in hardware until you are satisfied with its functionality and performance Some IP cores require that you pu...

Page 16: ...u to customize your IP core and manually integrate the function into your design Specifying Parameters To specify IP core parameters with the MegaWizard Plug In Manager follow these steps 1 Create a Quartus II project using the New Project Wizard available from the File menu Figure 2 2 Design Flows 1 Note to Figure 2 2 1 Altera IP cores may or may not support the Qsys and SOPC Builder design flows...

Page 17: ...s and encrypted RTL models and plain text RTL models These are all cycle accurate models The models allow for fast functional simulation of your IP core instance using industry standard VHDL or Verilog HDL simulators For some cores only the plain text RTL model is generated and you can simulate that model f For more information about functional simulation models for Altera IP cores refer to Simula...

Page 18: ...the generation process also creates complete example designs An example design for hardware testing is located in the variation_name _example_design example_project directory An example design for RTL simulation is located in the variation_name _example_design simulation directory 1 For information about the Quartus II software including virtual pins and the MegaWizard Plug In Manager refer to Qua...

Page 19: ...on about the 10GBASE R transceiver channel datapath clocking and channel placement refer to the 10GBASE R section in the Transceiver Protocol Configurations in Stratix V Devices chapter of the Stratix V Device Handbook Figure 3 2 illustrates a multiple 10 GbE channel IP core in a Stratix IV GT device To achieve higher bandwidths you can instantiate multiple channels The PCS is available in soft lo...

Page 20: ...rface This configuration does not require that all four channels in a quad run the 10GBASE R protocol Release Information Table 3 1 provides information about this release of the 10GBASE R PHY IP core Figure 3 2 Complete 10GBASE R PHY Design in Stratix IV GT Device To MAC To Embedded Controller Avalon MM connections 10GBase R PHY SDR XGMII 72 bits 156 25 Mbps To MAC SDR XGMII 72 bits 156 25 Mbps A...

Page 21: ...es Performance and Resource Utilization This section provides information on performance and resource utilization for Stratix IV and Stratix V devices Stratix IV Devices Table 3 3 shows the typical expected device resource utilization for duplex channels using the current version of the Quartus II software targeting a Stratix IV GT device The numbers of combinational ALUTs logic registers and memo...

Page 22: ...ing your own soft 10GBASE R PCS and connecting to the Low Latency PHY IP Core Parameter Settings To configure the 10GBASE R PHY IP core in the parameter editor click Installed Plug Ins Interfaces Ethernet 10GBASE R PHY v11 1 The 10GBASE R PHY IP core is available for the Stratix IV or Stratix V device family General Options This section describes the 10GBASE R PHY parameters which you can set usin...

Page 23: ...5 MHz Additional Options Use external PMA control and reconfig On Off For Stratix IV devices if you turn this option on the PMA controller and reconfiguration block are external rather than included 10GBASE R PHY IP core allowing you to use the same PMA controller and reconfiguration IP cores for other protocols in the same transceiver quad When you turn this option On the cal_blk_powerdown 0x021 ...

Page 24: ...ther or not the pre emphasis control signal for the pre tap is inverted If you turn this option on the pre emphasis control signal is inverted Pre emphasis first post tap setting 0 15 Sets the amount of pre emphasis for the 1st post tap Pre emphasis second post tap setting 0 7 Sets the amount of pre emphasis for the 2nd post tap Invert the pre emphasis second post tap polarity On Off Determines wh...

Page 25: ...ceiver pin Use External Resistor if you intend to use off chip termination 85_OHMS 100_OHMS 120_OHMS 150_OHMS EXTERNAL_ RESISTOR Pin XCVR_REFCLK_PIN_ TERMINATION Transceiver Dedicated Refclk Pin Termination Specifies the intended termination value for the specified refclk pin DC_COUPLING_ INTERNAL_100 _OHM DC_COUPLING_ EXTERNAL_ RESISTOR AC_COUPLING Pin XCVR_RX_BYPASS_EQ_ STAGES_234 Receiver Equal...

Page 26: ...ng the intended supply voltages for a GXB I O pin If your design uses decision feedback equalization DFE or adaptive equalization AEQ you must set this parameter to 1 0V Otherwise if you do not make this assignment the compiler automatically sets the correct VCCR_GXB and VCCT_GXB voltage depending on the configured data rate as follows Data rate 6 5 Gbps 0_85V Data rate 6 5 Gbps 1_0V 0_85V 1_0V Pi...

Page 27: ...trol is determined by the XCVR_RX_LINEAR_EQUALIZER_SETT ING assignment TRUE FALSE Pin XCVR_RX_EQ_BW_SEL Receiver Equalizer Gain Bandwidth Select Sets the gain peaking frequency for the equalizer For data rates of less than 6 5Gbps set to HALF For higher data rates set to FULL FULL HALF Pin XCVR_RX_SD_ENABLE Receiver Signal Detection Unit Enable Disable Enables or disables the receiver signal detec...

Page 28: ... Specifies the pre tap pre emphasis setting 0 15 Pin XCVR_TX_RX_DET_ENABLE Transmitter s Receiver Detect Block Enable Enables or disables the receiver detector circuit at the transmitter TRUE FALSE Pin XCVR_TX_RX_DET_MODE Transmitter s Receiver Detect Block Mode Sets the mode for receiver detect block 0 15 Pin XCVR_TX_RX_DET_OUTPUT_SEL Transmitter s Receiver Detect Block QPI PCI Express Control De...

Page 29: ... Show signals the block diagram displays all top level signal names f For more information about _hw tcl files refer to refer to the Component Interface Tcl Reference chapter in volume 1 of the Quartus II Handbook The following sections describe the signals in each interface Figure 3 3 10GBASE R PHY Top Level Signals f xgmii_tx_dc n 71 0 tx_ready xgmii_tx_clk xgmii_rx_dc n 71 0 rx_ready rx_data_re...

Page 30: ... for the mapping of the xgmii_tx_dc data and control to the xgmii_sdr_data and xgmii_sdr_ctrl signals tx_ready Output Asserted when the TX channel is ready to transmit data Because the readyLatency on this Avalon ST interface is 0 the MAC may drive tx_ready as soon as it comes out of reset xgmii_tx_clk Input The XGMII TX clock which runs at 156 25 MHz Note to Table 3 9 1 n is the channel number Ta...

Page 31: ...of data and 1 bit of control Lane 0 7 0 8 Lane 1 16 9 17 Lane 2 25 18 26 Lane 3 34 27 35 lane 4 43 36 44 Lane 5 52 45 53 Lane 6 61 54 62 Lane 7 70 63 71 Refer to Table 3 12 for the mapping of the xgmii_rx_dc data and control to the xgmii_sdr_data and xgmii_sdr_ctrl signals rx_ready Output Asserted when the RX reset is complete rx_data_ready n 1 0 Output When asserted indicates that the PCS is send...

Page 32: ...ane 0 control xgmii_rx_dc 16 9 xgmii_sdr_data 15 8 Lane 1 data xgmii_rx_dc 17 xgmii_sdr_ctrl 1 Lane 1 control xgmii_rx_dc 25 18 xgmii_sdr_data 23 16 Lane 2 data xgmii_rx_dc 26 xgmii_sdr_ctrl 2 Lane 2 control xgmii_rx_dc 34 27 xgmii_sdr_data 31 24 Lane 3 data xgmii_rx_dc 35 xgmii_sdr_ctrl 3 Lane 3 control xgmii_rx_dc 43 36 xgmii_sdr_data 39 32 Lane 4 data xgmii_rx_dc 44 xgmii_sdr_ctrl 4 Lane 4 cont...

Page 33: ... 257 8125 MHz clock Figure 3 4 illustrates the clock generation and distribution for Stratix IV devices Figure 3 4 Stratix IV GT Clock Generation and Distribution pll_ref_clk 644 53125 MHz 10 3125 Gbps serial 516 625 MHz 257 8125 MHz 516 625 MHz 257 8125 MHz 156 25 MHz 10GBASE R Transceiver Channel Stratix IV GT TX RX TX PCS hard IP TX PCS soft IP 20 40 64 TX PMA 2 10 3125 Gbps serial RX PCS hard ...

Page 34: ... MHz clock from the incoming data Table 3 15 describes the clock inputs Figure 3 5 Stratix V Clock Generation and Distribution pll_ref_clk 644 53125 MHz 10 3125 Gbps serial 257 8125 MHz 257 8125 MHz 156 25 MHz 10GBASE R Hard IP Transceiver Channel Stratix V TX RX TX PCS 40 64 TX PMA 10 3125 Gbps serial RX PCS 40 64 RX PMA TX PLL 8 33 fPLL xgmii_rx_clk xgmii_tx_clk Table 3 14 Clock Signals Signal N...

Page 35: ...andard The clock is embedded from the serial data stream Note to Table 3 15 1 n is the channel number Table 3 16 Avalon MM PHY Management Interface Signal Name Direction Description phy_mgmt_clk Input The clock signal that controls the Avalon MM PHY management interface For Stratix IV devices the frequency range is 37 5 50 MHz There is no frequency restriction for Stratix V devices however if you ...

Page 36: ... Options tab of the GUI 0x022 31 0 RO pma_tx_pll_is_locked Bit P indicates that the TX clock multiplier unit CMU PLL P is locked to the input reference clock This register is only available if you select Use external PMA control and reconfig on the Additional Options tab of the GUI Reset Control Registers Automatic Reset Controller 0x041 31 0 RW reset_ch_bitmask Reset controller channel bitmask fo...

Page 37: ... RW phy_serial_loopback Writing a 1 to channel n puts channel n in serial loopback mode For information about pre or post CDRserial loopback modes refer to Loopback Modes on page 10 39 0x064 31 0 RW pma_rx_set_locktodata When set programs the RX CDR PLL to lock to the incoming data Bit n corresponds to channel n 0x065 31 0 RW pma_rx_set_locktoref When set programs the RX CDR PLL to lock to the ref...

Page 38: ...received blocks From Block Block synchronizer 3 R TX_FIFO_FULL When asserted indicates the TX FIFO is full From block TX FIFO 4 R RX_FIFO_FULL When asserted indicates the RX FIFO is full From block RX FIFO 5 R RX_SYNC_HEAD_ERROR For Stratix V devices when asserted indicates an RX synchronization error This signal is Stratix V devices only 6 R RX_SCRAMBLER_ERROR For Stratix V devices when asserted ...

Page 39: ...ion clock For Stratix IV devices only It must be in the range 37 5 50 MHz You can use the same clock for the phy_mgmt_clk and the cal_blk_clk rx_recovered_clk n 0 Output This is the RX clock which is recovered from the received data stream reconfig_to_xcvr 3 0 Input Reconfiguration signals from the Transceiver Reconfiguration Controller to the PHY device This signal is only available in Stratix IV...

Page 40: ...ock Regions in Quartus II Help 1 For Stratix V devices timing constraints are built into the HDL code Example 3 2 provides the Synopsys Design Constraints File sdc timing constraints for the 10GBASE R IP core To pass timing analysis you must decouple the clocks in different time domains Be sure to verify the each clock domain is correctly buffered in the top level of your design You can find the s...

Page 41: ...ceive_pcs clkout to pll_ref_clk hold 0 1 set_clock_uncertainty from get_clocks siv_alt_pma pma_direct auto_generated transmit_pcs0 clkout to pll_ref_clk hold 0 08 Set Input Delay Set Output Delay Set Clock Groups set_clock_groups exclusive group phy_mgmt_clk group xgmii_tx_clk group get_clocks siv_alt_pma pma_ch pma_direct transmit_pcs clkout group get_clocks siv_alt_pma pma_ch pma_direct receive_...

Page 42: ...rect receive_pcs clkout siv_alt_pma pma_ch pma_direct transmit_pcs clkout pll_siv_xgmii_clk altpll_component auto_generated pll1 clk 0 phy_mgmt_clk xgmii_tx_clk set_false_path from siv_10gbaser_xcvr clk_reset_ctrl tx_usr_rstn to get_clocks siv_alt_pma pma_ch pma_direct receive_pcs clkout siv_alt_pma pma_ch pma_direct transmit_pcs clkout pll_siv_xgmii_clk altpll_component auto_generated pll1 clk 0 ...

Page 43: ...AUI PHY IP core For Stratix IV GX and GT devices you can choose a hard XAUI physical coding sublayer PCS and physical media attachment PMA or a soft XAUI PCS and PMA in low latency mode You can also combine both hard and soft PCS configurations in the same device using all channels in a transceiver bank The PCS is only available in soft logic for Stratix V devices f For more detailed information a...

Page 44: ...core for Altera device families Table 4 1 XAUI Release Information Item Description Version 11 1 Release Date November 2011 Ordering Codes 1 IP XAUIPCS primary Soft PCS IPR XAUIPCS renewal Soft PCS Product ID 00D7 Vendor ID 6AF7 Note to Table 4 1 1 No ordering codes or license files are required for the hard PCS and PMA PHY in Arria II GX Cyclone IV GX or Stratix IV GX or GT devices Table 4 2 Devi...

Page 45: ...annel 0 of this XAUI PHY In Arria II GX Cyclone IV GX HardCopy IV and Stratix IV devices this starting channel number must be 0 or a multiple of 4 There are no numbering restrictions for Stratix V devices Assignment of the starting channel number is required for serial transceiver dynamic reconfiguration XAUI interface type Hard XAUI Soft XAUI DDR XAUI The following 3 interface types are available...

Page 46: ...OHMS OCT_100_OHMS OCT_120_OHMS OCT_150_OHMS Indicates the value of the termination resistor for the transmitter Transmitter VOD control setting 0 7 Sets VOD for the various TX buffers Pre emphasis pre tap setting 0 7 Sets the amount of pre emphasis on the TX buffer Available for Stratix IV Invert the pre emphasis pre tap polarity setting On Off Determines whether or not the pre emphasis control si...

Page 47: ...tion In Table 4 6 the default value of an analog parameter is shown in bold type Receiver DC gain 0 4 Sets the equalization DC gain using one of the following settings 0 0 dB 1 3 dB 2 6 dB 3 9 dB 4 12 dB Receiver static equalizer setting 0 15 This option sets the equalizer control settings The equalizer uses a pass band filter Specifying a low value passes low frequencies Specifying a high value p...

Page 48: ...tage for a GXB I O pin If you do not make this assignment the compiler automatically sets the correct VCCA_GXB voltage depending on the configured data rate as follows Data rate 6 5 Gbps 2_5V Data rate 6 5 Gbps 3_0V or 3_3V for Stratix V ES silicon 2_5V 3_0V Pin XCVR_VCCR_VCCT_VOLTAGE VCCR_GXB VCCT_GXB Voltage Configure the VCCR_GXB and VCCT_GXB voltage for an GXB I O pin by specifying the intende...

Page 49: ...h preset setting Auto Low Medium High PLL instance XCVR_RX_DC_GAIN Receiver Buffer DC Gain Control Controls the amount of a stage receive buffer DC gain 0 4 Pin XCVR_RX_LINEAR_EQUALIZER_ CONTROL Receiver Linear Equalizer Control Static control for the continuous time equalizer in the receiver buffer The equalizer has 16 distinct settings from 0 15 corresponding to the increasing AC gain 1 16 Pin A...

Page 50: ...T_0P50V VOLT_0P35V PULL_UP PULL_DOWN TRISTATED1 GROUNDED PULL_UP_TO VCCELA TRISTATED2 TRISTATED3 TRISTATED4 Pin XCVR_TX_PRE_EMP_1ST_POST_ TAP Transmitter Preemphasis First Post Tap Specifies the first post tap setting value 0 31 Pin XCVR_TX_PRE_EMP_2ND_ POST_TAP Transmitter Preemphasis Second Post Tap Specifies the second post tap setting value 0 15 Pin XCVR_TX_PRE_EMP_INV_ 2ND_TAP Transmitter Pre...

Page 51: ...ices Sheet 1 of 3 QSF Assignment Name Pin Planner and Assignment Editor Name Description Options Assign To Table 4 8 Advanced Options Name Value Description Include control and status ports On Off If you turn this option on the top level IP core include the status signals and digital resets shown in Figure 4 4 on page 4 12 and Figure 4 3 on page 4 11 If you turn this option off you can access cont...

Page 52: ...roller must always be external Refer to Chapter 10 Transceiver Reconfiguration Controller for more information about this IP core Interfaces This section describes interfaces of the XAUI PHY IP Core It includes the following topics Ports Registers Dynamic Reconfiguration Figure 4 2 XAUI PHY with Internal Transceiver Reconfiguration Control System Interconnect Fabric System Interconnect Fabric Inte...

Page 53: ... for the hard IP implementation which is available for Arria II GX Cyclone IV GX HardCopy IV and Stratix IV GX devices Figure 4 3 XAUI Top Level Signals Hard IP PCS and PMA xgmii_tx_dc 71 0 xgmii_tx_clk xgmii_rx_dc 71 0 xgmii_rx_clk phy_mgmt_clk phy_mgmt_clk_reset phy_mgmt_address 8 0 phy_mgmt_writedata 31 0 phy_mgmt_readdata 31 0 phy_mgmt_write phy_mgmt_read phy_mgmt_waitrequest pll_ref_clk rx_an...

Page 54: ... is eight bytes wide with eight control bits instead of the standard four bytes of data and four bits of control The XAUI IP core treats the datapath as two 32 bit data buses and includes logic to interleave them starting with the low order bytes Figure 4 5 illustrates the mapping Figure 4 4 XAUI Top Level Signals Soft PCS and PMA xgmii_tx_dc 71 0 xgmii_tx_clk xmii_rx_dc 71 0 xgmii_rx_clk phy_mgmt...

Page 55: ...ransmission Example tx_clk txc 7 0 txd 7 0 txd 31 8 txd 39 32 txd 55 40 txd 63 56 FF 01 00 F0 FF start FB AAAA AA frame data frame data frame data terminate FD frame data sfd AB frame data AAAAAA preamble preamble preamble Figure 4 7 Byte 4 Start of Frame Transmission Example tx_clk txc 7 0 txd 7 0 txd 23 8 txd 31 24 txd 39 32 txd 55 40 txd 63 56 FF 1F 00 F8 FF 07 AA frame data 0707 AAAA AAAA AA f...

Page 56: ... xgmii_tx_dc 71 0 Source Contains 4 lanes of data and control for XGMII Each lane consists of 16 bits of data and 2 bits of control Lane 0 7 0 8 43 36 44 Lane 1 16 9 17 52 45 53 Lane 2 25 18 26 61 54 62 Lane 3 34 27 35 70 63 71 xgmii_tx_clk Input The XGMII SDR TX clock which runs at 156 25 MHz or 312 5 for the DDR variant Table 4 10 SDR RX XGMII Interface Signal Name Direction Description xgmii_rx...

Page 57: ...PCS XAUI Hard IP Core 4 x 3 125 Gbps serial Hard PCS tx_coreclk rx_cruclk pll_inclk coreclkout xgmii_rx_clk xgmii_tx_clk pll_ref_clk phy_mgmt_clk 4 4 PMA XAUI Soft IP Core 4 x 3 125 Gbps serial xgmii_rx_clk xgmii_tx_clk pll_ref_clk phy_mgmt_clk 4 4 Soft PCS pma_pll_inclk pma_tx_clkout tx_clkout pma_rx_clkout pll_ref_clk sysclk PMA rx_recovered_clk Table 4 12 Clock and Reset Signals Signal Name Dir...

Page 58: ...s pll_locked Output Indicates CMU PLL is locked Only available in Arria II GX and Stratix IV GX and Stratix IV GT devices rx_recovered_clk 3 0 Output This is the RX clock which is recovered from the received data stream rx_ready Output Indicates PMA RX has exited the reset state and the transceiver can receive data tx_ready Output Indicates PMA TX has exited the reset state and the transceiver can...

Page 59: ...to the received data rx_is_lockedtodata 3 0 Output When asserted indicates the RX channel is locked to input data rx_set_locktoref 3 0 Input Force the receiver CDR to lock to the phase and frequency of the input reference clock rx_is_lockedtoref 3 0 Output When asserted indicates the RX channel is locked to input reference clock tx_invpolarity 3 0 input Dynamically reverse the polarity the data wo...

Page 60: ...d when the rate match block inserts a R column The flag is asserted for one clock cycle per inserted R column rx_runningdisp 7 0 Output Asserted when the current running disparity of the 8B 10B decoded byte is negative Low when the current running disparity of the 8B 10B decoded byte is positive rx_syncstatus 7 0 Output Synchronization indication RX synchronization is indicated on the rx_syncstatu...

Page 61: ...ust restrict the frequency range of phy_mgmt_clk to 100 125 MHz to meet the specification for the transceiver reconfiguration clock For Arria II GX Cyclone IV GX HardCopy IV and Stratix IV GX the frequency range is 37 5 50 MHz phy_mgmt_clk_reset Input Global reset signal that resets the entire XAUI PHY This signal is active high and level sensitive phy_mgmt_addr 8 0 Input 9 bit Avalon MM address p...

Page 62: ... internal RX analog reset signal to be asserted resetting the RX analog logic of all channels enabled in reset_ch_bitmask You must write a 0 to clear the reset condition 3 RW reset_rx_digital Writing a 1 causes the RX digital reset signal to be asserted resetting the RX digital channels enabled in reset_ch_bitmask You must write a 0 to clear the reset condition PMA Control and Status Registers 0x0...

Page 63: ...ponding bit The RX sync status register has 2 bits per channel for a total of 8 bits per hard XAUI link The RX sync status register has 1 bit per channel for a total of 4 bits per soft XAUI link soft XAUI uses bits 0 3 Reading the value of the syncstatus register clears the bits From block Word aligner 0x085 31 16 Reserved 15 8 R errdetect 7 0 When set indicates that a received 10 bit code group h...

Page 64: ...alue of the rmfifodatainserted register clears the bits This register is only available in the hard XAUI implementation From block Rate match FIFO 7 0 rmfifodatadeleted 7 0 When asserted indicates that the rate match block has deleted an R column The flag goes high for one clock cycle per deleted R column There are 2 bits for each lane Reading the value of the rmfifodatadeleted register clears the...

Page 65: ...tion interface If your XAUI PHY IP core includes a single transceiver quad these signals are internal to the core If your design uses more than one quad the reconfiguration signals are external 0x089 31 3 Reserved 2 0 R sticky phase_comp_fifo_error 2 0 Indicates a TX phase compensation FIFO overflow or underrun condition on the corresponding lane Reading the value of the phase_comp_fifo_error regi...

Page 66: ... design typically includes a reconfiguration interface for three channels Allowing the Quartus II software to merge reconfiguration interfaces gives the Fitter more flexibility in placing transceiver channels Simulation Files and Example Testbench Refer to Running a Simulation Testbench on page 1 4 for a description of the directories and files that the Quartus II software creates automatically wh...

Page 67: ...iming diagrams refer to the Avalon Interface Specifications Interlaken operates on 64 bit data words and 3 control bits which are striped round robin across the lanes to reduce latency Striping renders the interface independent of exact lane count The protocol accepts packets on 256 logical channels and is expandable to accommodate up to 65 536 logical channels Packets are split into small bursts ...

Page 68: ...IP core for Altera device families Parameter Settings To configure the Interlaken PHY IP core in the parameter editor click Installed Plug Ins Interfaces Interlaken Interlaken PHY v11 1 The Interlaken PHY IP core is only available when you select the Stratix V device family General Options Table 5 2 describes the parameters that you can set on the General tab Table 5 1 Device Family Support Device...

Page 69: ...to minimize the number of PLLs required to generate the clocks necessary for data transmission at different frequencies Depending on the Lane rate you specify the default Base data rate can be either 1 2 or 4 times the Lane rate however you can change this value The default value specified is for backwards compatibility with earlier Quartus II software releases Table 5 2 General Option Part 2 of 2...

Page 70: ...efault value of an analog parameter is shown in bold type Table 5 4 Transceiver and PLL Assignments for Stratix V Devices Sheet 1 of 2 QSF Assignment Name Pin Planner and Assignment Editor Name Description Options Assign To XCVR_IO_PIN_TERMINATION Transceiver I O Pin Termination Specifies the intended on chip termination value for the specified transceiver pin Use External Resistor if you intend t...

Page 71: ...ing the intended supply voltages for a GXB I O pin If your design uses decision feedback equalization DFE or adaptive equalization AEQ you must set this parameter to 1 0V Otherwise if you do not make this assignment the compiler automatically sets the correct VCCR_GXB and VCCT_GXB voltage depending on the configured data rate as follows Data rate 6 5 Gbps 0_85V Data rate 6 5 Gbps 1_0V 0_85V 1_0V P...

Page 72: ...trol is determined by the XCVR_RX_LINEAR_EQUALIZER_SETT ING assignment TRUE FALSE Pin XCVR_RX_EQ_BW_SEL Receiver Equalizer Gain Bandwidth Select Sets the gain peaking frequency for the equalizer For data rates of less than 6 5Gbps set to HALF For higher data rates set to FULL FULL HALF Pin XCVR_RX_SD_ENABLE Receiver Signal Detection Unit Enable Disable Enables or disables the receiver signal detec...

Page 73: ... Specifies the pre tap pre emphasis setting 0 15 Pin XCVR_TX_RX_DET_ENABLE Transmitter s Receiver Detect Block Enable Enables or disables the receiver detector circuit at the transmitter TRUE FALSE Pin XCVR_TX_RX_DET_MODE Transmitter s Receiver Detect Block Mode Sets the mode for receiver detect block 0 15 Pin XCVR_TX_RX_DET_OUTPUT_SEL Transmitter s Receiver Detect Block QPI PCI Express Control De...

Page 74: ...nd places the interface name inside the box The interface type and name are used to define interfaces in the _hw tcl writing Figure 5 2 Top Level Interlaken PHY Signals 1 Note to Figure 5 2 1 n the number of channels in the interface so that the width of tx_data in 4 channel instantiation is 263 0 tx_parallel_data n 65 0 tx_ready tx_datain_bp n tx_clkout n tx_user_clkout pll_locked tx_sync_done rx...

Page 75: ... tx_parallel_data n 63 0 is valid and is ready to be written into the TX FIFO When deasserted indicates that tx_parallel_data n 63 0 is invalid and is not written into the TX FIFO The Interlaken MAC should gate tx_parallel_data n 65 based on tx_datain_bp n tx_ready Source When asserted indicates that the TX interface has exited the reset state and is ready for service The tx_ready latency for the ...

Page 76: ... to the FPGA fabric rx_parallel_data n 64 Source When asserted indicates that rx_parallel_data n 63 0 is valid When deasserted indicates the rx_parallel_data n 63 0 is invalid The Interlaken PCS implements a gearbox between the PMA and PCS interface The rx_parallel_data n 64 port is deasserted whenever the gearbox is in the invalid region The Interlaken MAC should gate rx_dataout_bp n usage based ...

Page 77: ...gnal may be asserted after the frame synchronizer state machine validates frame synchronization and asserts rx_parallel_data n 70 because this signal is asserted by the RX FIFO which is the last PCS block in the RX datapath This signal is optional If the RX PCS FIFO reaches the empty state or is in an empty state rx_parallel_data n 70 indicating metaframe lock and rx_parallel_data n 69 indicating ...

Page 78: ... 5 7 Avalon ST RX Signals Part 3 of 3 Signal Name Direction Description Table 5 8 Serial Interface Signal Name Direction Description pll_ref_clk Input Reference clock for the PHY PLLs Refer to the Lane rate entry in Table 5 2 on page 5 2 for required frequencies Table 5 9 Serial Interface Signal Name Direction Description tx_serial_data Output Differential high speed serial output data using the P...

Page 79: ...ce and transceiver reconfiguration you must restrict the frequency range of phy_mgmt_clk to 100 125 MHz to meet the specification for the transceiver reconfiguration clock phy_mgmt_clk_reset Input Global reset signal that resets the entire Interlaken PHY Changed definition of phy_mgmt_clk_reset This signal is active high and level sensitive phy_mgmt_addr 8 0 Input 9 bit Avalon MM address phy_mgmt_...

Page 80: ...ll channels enabled in reset_ch_bitmask You must write a 0 to clear the reset condition 1 RW reset_tx_digital Writing a 1 causes the internal TX digital reset signal to be asserted resetting all channels enabled in reset_ch_bitmask You must write a 0 to clear the reset condition PMA Control and Status Registers 0x061 31 0 RW phy_serial_loopback Writing a 1 to channel n puts channel n in serial loo...

Page 81: ...cludes a reconfiguration interface for three channels Allowing the Quartus II software to merge reconfiguration interfaces gives the Fitter more flexibility in placing transceiver channels For more information about transceiver reconfiguration refer to Chapter 10 Transceiver Reconfiguration Controller Stratix V Device Registers 27 R rx_crc32_err Asserted by the CRC32 checker to indicate a CRC erro...

Page 82: ...s II software creates automatically when you generate your Interlaken PHY IP core f Refer to the Altera wiki for an example testbench that you can use as a starting point in creating your own verification environment Table 5 13 Reconfiguration Interface Signal Name Direction Description reconfig_to_xcvr n 70 1 0 Sink Reconfiguration signals from the Transceiver Reconfiguration Controller n grows l...

Page 83: ...ion in the Transceiver Protocol Configurations in Stratix V Devices chapter of the Stratix V Device Handbook Device Family Support IP cores provide either final or preliminary support for target Altera device families These terms have the following definitions Final support Verified with final timing models for this device Preliminary support Verified with preliminary timing models for this device...

Page 84: ...I Express PHY PIPE Performance and Resource Utilization Stratix V Devices Number of Lanes Combinational ALUTs Logic Registers Memory Bits PLLs Gen1 1 460 285 0 2 Gen1 4 530 373 0 5 Gen1 8 590 425 0 9 Gen2 1 460 295 0 2 Gen2 4 530 373 0 5 Gen2 8 590 425 0 9 Table 6 3 General Options Part 1 of 2 Name Value Description Device family Stratix V Supports only Stratix V devices Number of lanes 1 4 8 The ...

Page 85: ...arrower range of data rates and reference clock frequencies For example if a base data rate of 2500 Mbps is not available with the ATX PLL and a 100 MHz reference clock however base data rates of 5000 Mbps or 10000 Mbps are possible with the ATX PLL and 100 MHz reference clock Another advantage of the ATX PLL is that it does not use a transceiver channel while the CMU PLL does PLL reference clock ...

Page 86: ...transceiver pin Use External Resistor if you intend to use off chip termination 85_OHMS 100_OHMS 120_OHMS 150_OHMS EXTERNAL_ RESISTOR Pin XCVR_REFCLK_PIN_ TERMINATION Transceiver Dedicated Refclk Pin Termination Specifies the intended termination value for the specified refclk pin DC_COUPLING_ INTERNAL_100 _OHM DC_COUPLING_ EXTERNAL_ RESISTOR AC_COUPLING Pin XCVR_RX_BYPASS_EQ_ STAGES_234 Receiver ...

Page 87: ...ecifying the intended supply voltages for a GXB I O pin If your design uses decision feedback equalization DFE or adaptive equalization AEQ you must set this parameter to 1 0V Otherwise if you do not make this assignment the compiler automatically sets the correct VCCR_GXB and VCCT_GXB voltage depending on the configured data rate as follows Data rate 6 5 Gbps 0_85V Data rate 6 5 Gbps 1_0V 0_85V 1...

Page 88: ...n control is determined by the XCVR_RX_LINEAR_EQUALIZER_SETT ING assignment TRUE FALSE Pin XCVR_RX_EQ_BW_SEL Receiver Equalizer Gain Bandwidth Select Sets the gain peaking frequency for the equalizer For data rates of less than 6 5Gbps set to HALF For higher data rates set to FULL FULL HALF Pin XCVR_RX_SD_ENABLE Receiver Signal Detection Unit Enable Disable Enables or disables the receiver signal ...

Page 89: ...e Tap Specifies the pre tap pre emphasis setting 0 15 Pin XCVR_TX_RX_DET_ENABLE Transmitter s Receiver Detect Block Enable Enables or disables the receiver detector circuit at the transmitter TRUE FALSE Pin XCVR_TX_RX_DET_MODE Transmitter s Receiver Detect Block Mode Sets the mode for receiver detect block 0 15 Pin XCVR_TX_RX_DET_OUTPUT_SEL Transmitter s Receiver Detect Block QPI PCI Express Contr...

Page 90: ...ation interface r is automatically calculated based on the selected configuration pipe_txdata n d 1 0 pipetx_datak n d 8 1 0 pipe_rxdata n d 1 0 pipe_rxdatak n d 8 1 0 pipe_rxvalid n 1 0 phy_mgmt_clk phy_mgmt_clk_reset phy_mgmt_address 8 0 phy_mgmt_writedata 31 0 phy_mgmt_readdata 31 0 phy_mgmt_write phy_mgmt_read phy_mgmt_waitrequest pll_ref_clk fixedclk pipe_pclk pipe_txdetectrx_loopback n 1 0 p...

Page 91: ...PHYMAC Table 6 7 describes the signals in the Avalon ST output interface These signals are driven from the PHY to the PHYMAC This is an Avalon source interface Table 6 6 Avalon ST TX Inputs Signal Name Dir Description pipe_txdata n d 1 0 Sink This is TX parallel data driven from the PHYMAC for PCI Express The ready latency on this interface is 0 so that the PHY must be able to accept data as soon ...

Page 92: ... This clock can be derived from pll_ref_clk pipe_txdetectrx_loopback Sink This signal instructs the PHY to start a receive detection operation After power up asserting this signal starts a loopback operation Refer to section 6 4 of the Intel PHY Interface for PCI Express PIPE Architecture for a timing diagram pipe_txelecidle Sink This signal forces the transmit output to electrical idle Refer to s...

Page 93: ...rce This signal encodes receive status and error codes for the receive data stream and receiver detection The following encodings are defined 000 receive data OK 001 1 SKP added 010 1 SKP removed 011 Receiver detected 100 Both 8B 10B decode error and optionally RX disparity error 101 Elastic buffer overflow 110 Elastic buffer underflow 111 Receive disparity error rx_eidleinfersel n 1 0 Sink When a...

Page 94: ...50 MHz Gen1 500 MHz Gen2 pipe_rate pipe_phystatus n 1 0 T1 T1 Table 6 9 Transceiver Differential Serial Interface Signal Name Direction Description rx_serial_data n 1 0 Input Receiver differential serial input data n is the number of lanes tx_serial_data n 1 0 Output Transmitter differential serial output data n is the number of lanes Table 6 10 Status Signals Part 1 of 2 1 Signal Name Direction S...

Page 95: ...am rx_signaldetect d n 8 1 0 Output When asserted indicates that the lane detects a sender at the other end of the link Note to Table 6 10 1 n is the number of lanes d is the deserialization factor p is the number of PLLs Table 6 10 Status Signals Part 2 of 2 1 Signal Name Direction Signal Name Figure 6 4 PCI Express PIPE IP Core 1 Note to Figure 6 4 1 Blocks in gray are soft logic Blocks in white...

Page 96: ...iver reconfiguration clock phy_mgmt_clk_reset Input Global reset signal that resets the entire PHY IP core Changed definition of phy_mgmt_clk_reset This signal is active high and level sensitive phy_mgmt_address 8 0 Input 9 bit Avalon MM address phy_mgmt_writedata 31 0 Input Input data phy_mgmt_readdata 31 0 Output Output data phy_mgmt_write Input Write signal phy_mgmt_read Input Read signal phy_m...

Page 97: ...uses the internal RX digital reset signal to be asserted resetting the RX analog logic of all channels enabled in reset_ch_bitmask You must write a 0 to clear the reset condition 1 RW reset_tx_digital Writing a 1 causes the internal TX digital reset signal to be asserted resetting all channels enabled in reset_ch_bitmask You must write a 0 to clear the reset condition 0 RW pll_powerdown Writing a ...

Page 98: ...he number of bits slipped by the RX Word Aligner to achieve word alignment Used for very latency sensitive protocols From block Word aligner 0 R rx_phase_comp_fifo_error When set indicates an RX phase compensation FIFO error From block RX phase compensation FIFO 0x082 31 1 R Reserved 0 RW tx_phase_comp_fifo_error When set indicates a TX phase compensation FIFO error From block TX phase compensatio...

Page 99: ...r 0 RW rx_enapatternalign When set the word alignment logic operates in pattern detect mode To block Word aligner 0x086 31 20 R Reserved 19 16 R rx_rlv When set indicates a run length violation From block Word aligner 15 12 R rx_patterndetect When set indicates that RX word aligner has achieved synchronization From block Word aligner 11 8 R rx_disperr When set indicates that the received 10 bit co...

Page 100: ...his interface uses the Avalon MM PHY Management interface clock Simulation Files and Example Testbench Refer to Running a Simulation Testbench on page 1 4 for a description of the directories and files that the Quartus II software creates automatically when you generate your PHY IP core for PCI Express f Refer to the Altera wiki for an example testbench that you can use as a starting point in crea...

Page 101: ...u can configure the Custom PHY IP core to support many standard protocols including all of the following protocols Serial Data Converter SDC JESD204A Serial digital interface SDI Ethernet GbE Serial RapidIO SRIO 1 3 Serial ATA SATA and sequential active serial SAS Gen1 Gen2 and Gen3 Gigabit capable passive optical network GPON Your MAC layer must use the Avalon ST to transmit and receive data from...

Page 102: ...d by the Custom PHY IP core for Altera device families Performance and Resource Utilization Because the PCS and PMA are both implemented in hard logic the Custom PHY IP core requires less than 1 of FPGA resources Table 7 1 lists the resource utilization for the Custom PHY when the 1 25GbE preset is specified Figure 7 1 Custom PHY IP Core Custom PHY IP Core Tx Serial Data Avalon ST Tx and Rx Rx Ser...

Page 103: ...Mode of operation Duplex TX RX You can select to transmit data receive data or both Number of lanes 1 32 The total number of lanes in each direction Enable lane bonding On Off When enabled a single clock drives multiple lanes reducing clock skew In Stratix V devices up to 6 lanes can be bonded if you use an ATX PLL 5 lanes can be bonded If you select the CMU PLL Bonding mode N fb_compensation Sele...

Page 104: ...00 Mbps Specifies the data rate Base data rate 1 Lane rate 2 Lane rate 4 Lane rate The base data rate is the frequency of the clock input to the PLL Select a base data rate that minimizes the number of PLLs required to generate all the clocks required for data transmission By selecting an appropriate base data rate you can change data rates by changing the divider used by the clock generation bloc...

Page 105: ...set and pll_powerdown which are top level ports of the Custom Transceiver PHY You must turn this option Off to implement your own reset controller By default the CDR circuitry is in automatic lock mode whether you use the embedded reset controller or design your own reset logic You can switch the CDR to manual mode by writing the pma_rx_setlocktodata or pma_rx_set_locktoref registers to 1 If eithe...

Page 106: ... earliest received bit from the received data Automatic synchronization state machine Automatic synchronization state machine In this mode word alignment is controlled by a programmable state machine This mode can only be used with 8B 10B encoding The data width at the word aligner can be 10 or 20 bits You can specify the following parameters Number of consecutive valid words before sync state is ...

Page 107: ...gnment Mode Word Alignment Pattern Length bits Word Alignment Behavior Custom single deserializer width 8 Manual alignment 16 User controlled signal starts alignment process Alignment occurs once unless signal is re asserted 10 Manual alignment 7 10 User controlled signal starts alignment process Alignment occurs once unless signal is re asserted Automatic synchronized state machine Data must be 8...

Page 108: ...ptional rate match FIFO status ports On Off When enabled creates the rx_rmfifoddatainserted and rx_rmfifodatadeleted signals from the rate match FIFO become output ports Table 7 7 Rate Match FIFO Options Part 2 of 2 Name Value Description Table 7 8 8B 10B Options Name Value Description Enable 8B 10B decoder encoder On Off Enable this option if your application requires 8B 10B encoding and decoding...

Page 109: ... PLL reconfiguration Number of TX PLLs 1 4 Specifies the number of TX PLLs required for this instance of the Custom PHY More than 1 PLL may be required if your design reconfigures channels to run at multiple frequencies Number of input clocks 1 5 Specifies the number of input reference clocks More than one reference clock may be required if your design reconfigures channels to run at multiple freq...

Page 110: ... Interface Enable channel interface On Off Turn this option on to enable PLL and datapath dynamic reconfiguration When you select this option the width of tx_parallel_data and rx_parallel_data buses increases in the following way The tx_parallel_data bus is 44 bits per lane however only the low order number of bits specified by the FPGA fabric transceiver interface width contain valid data for eac...

Page 111: ...ltage for a GXB I O pin If you do not make this assignment the compiler automatically sets the correct VCCA_GXB voltage depending on the configured data rate as follows Data rate 6 5 Gbps 2_5V Data rate 6 5 Gbps 3_0V or 3_3V for Stratix V ES silicon 2_5V 3_0V Pin XCVR_VCCR_VCCT_VOLTAGE VCCR_GXB VCCT_GXB Voltage Configure the VCCR_GXB and VCCT_GXB voltage for an GXB I O pin by specifying the intend...

Page 112: ...idth preset setting Auto Low Medium High PLL instance XCVR_RX_DC_GAIN Receiver Buffer DC Gain Control Controls the amount of a stage receive buffer DC gain 0 4 Pin XCVR_RX_LINEAR_EQUALIZER_ CONTROL Receiver Linear Equalizer Control Static control for the continuous time equalizer in the receiver buffer The equalizer has 16 distinct settings from 0 15 corresponding to the increasing AC gain 1 16 Pi...

Page 113: ...LT_0P50V VOLT_0P35V PULL_UP PULL_DOWN TRISTATED1 GROUNDED PULL_UP_TO VCCELA TRISTATED2 TRISTATED3 TRISTATED4 Pin XCVR_TX_PRE_EMP_1ST_POST_ TAP Transmitter Preemphasis First Post Tap Specifies the first post tap setting value 0 31 Pin XCVR_TX_PRE_EMP_2ND_ POST_TAP Transmitter Preemphasis Second Post Tap Specifies the second post tap setting value 0 15 Pin XCVR_TX_PRE_EMP_INV_ 2ND_TAP Transmitter Pr...

Page 114: ... Transmitter Differential Output Voltage Differential output voltage setting The values are monotonically increasing with the driver main tap current strength 0 63 50 Pin XCVR_TX_VOD_PRE_EMP_ CTRL_SRC Transmitter VOD Preemphasis Control Source When set to DYNAMIC_CTL the PCS block controls the VOD and preemphasis coefficients for PCI Express When this assignment is set to RAM_CTL the VOD and preem...

Page 115: ...onsecutive valid words before sync state is reached 1 Number of bad data words before loss of sync state 1 Number of valid patterns before sync state is reached 10 Create optional word aligner status ports Off Word aligner pattern length 10 Word alignment pattern 1011111100 Enable run length violation checking Off Run length 40 Rate Match Options Enable rate match FIFO On Rate match insertion dele...

Page 116: ...w s 1 0 rx_parallel_data n w 1 0 rx_clkout n 1 0 rx_datak n w s 1 0 rx_runningdisp n w s 1 0 rx_enabyteordflag n 1 0 phy_mgmt_clk phy_mgmt_clk_reset phy_mgmt_address 8 0 phy_mgmt_writedata 31 0 phy_mgmt_readdata 31 0 phy_mgmt_write phy_mgmt_read phy_mgmt_waitrequest pll_ref_clk rx_coreclkin n 1 0 tx_coreclkin n 1 0 Custom PHY Top Level Signals tx_serial_data n 1 0 rx_serial_data n 1 0 tx_ready rx_...

Page 117: ...is control tx_forcedisp n w s 1 0 Sink When asserted this control signal enables disparity to be forced on the TX channel This signal is created if you turn On the Enable manual disparity control option on the 8B 10B tab tx_dispval n w s 1 0 Sink This control signal specifies the disparity of the data This port is created if you turn On the Enable disparity control option on the 8B 10B tab Table 7...

Page 118: ...ut Transmitter differential serial output data Note to Table 7 17 1 n is the number of lanes w is the PCS to FPGA fabric interface width s is the symbol size in bits p is the number of PLLs Table 7 18 Serial Interface and Status Signals Part 1 of 2 1 Signal Name Direction Signal Name tx_ready Output When asserted indicates that the TX interface has exited the reset state and is ready to transmit r...

Page 119: ...d aligner slips a bit of the current word for every rising edge of this signal rx_bitslipboundaryselectout n 5 1 0 Output This signal is used for bit slip word alignment mode It reports the number of bits that the RX block slipped to achieve a deterministic latency rx_patterndetect n w s 1 0 Output When asserted indicates that the programmed word alignment pattern has been detected in the current ...

Page 120: ... resets the RX CDR rx_cal_busy n 1 0 Output When asserted indicates that the RX channel is being calibrated You must hold the channel in reset until calibration completes Table 7 19 Avalon ST RX Interface Part 2 of 2 Signal Name Direction Description Figure 7 3 Custom PHY IP Core 1 Note to Figure 7 3 1 Blocks in gray are soft logic Blocks in white are hard logic System Interconnect Fabric System I...

Page 121: ...tion for the transceiver reconfiguration clock phy_mgmt_clk_reset Input Global reset signal This signal is active high and level sensitive phy_mgmt_address 8 0 Input 9 bit Avalon MM address phy_mgmt_writedata 31 0 Input Input data phy_mgmt_readdata 31 0 Output Output data phy_mgmt_write Input Write signal phy_mgmt_read Input Read signal phy_mgmt_waitrequest Output When asserted indicates that the ...

Page 122: ...to 1 31 4 0 RW Reserved It is safe to write 0s to reserved bits 3 RW reset_rx_digital Writing a 1 causes the internal RX digital reset signal to be asserted resetting the RX digital channels enabled in reset_ch_bitmask You must write a 0 to clear the reset condition 2 RW reset_rx_analog Writing a 1 causes the internal RX analog reset signal to be asserted resetting the RX analog logic of all chann...

Page 123: ...cates an RX phase compensation FIFO error From block RX phase Compensation FIFO 0x082 0 RW tx_phase_comp_fifo_error When set indicates an TX phase compensation FIFO error From block TX phase Compensation FIFO 0x083 5 1 RW tx_bitslipboundary_select Sets the number of bits that the TX bit slipper needs to slip To block Word aligner 0 RW tx_invpolarity When set the TX interface inverts the polarity o...

Page 124: ...s gives the Fitter more flexibility in placing transceiver channels For more information about transceiver reconfiguration refer to Chapter 10 Transceiver Reconfiguration Controller Table 7 22 describes the signals in the reconfiguration interface This interface uses the Avalon MM PHY Management interface clock Simulation Files and Example Testbench Refer to Running a Simulation Testbench on page ...

Page 125: ...interface An Avalon MM interface provides access to control and status information Figure 8 1 illustrates the top level modules of the Low Latency PHY IP core Because the Low latency PHY IP core bypasses much of the PCS it minimizes the PCS latency f For more detailed information about the Low Latency datapath and clocking refer to the refer to the Stratix V GX Device Configurations section in the...

Page 126: ...able 8 2 Low Latency PHY Performance and Resource Utilization Stratix V GX Device Implementation Number of Lanes Serialization Factor Worst Case Frequency Combinational ALUTs Dedicated Registers Memory Bits 11 Gbps 1 32 or 40 599 16 112 95 0 11 Gbps 4 32 or 40 584 8 141 117 0 11 Gbps 10 32 or 40 579 71 192 171 0 6 Gbps 10 Gbps datapath 1 32 or 40 608 27 111 93 0 6 Gbps 10 Gbps datapath 4 32 or 40 ...

Page 127: ... RX or TX mode Number of lanes 1 32 1 4 Specifies the total number of lanes in each direction Stratix V devices include up to 32 GX channels Standard or 10G and up to 4 GT channels You must instantiate each GT channel in a separate Low Latency PHY IP core instance You cannot specify both GX and GT channels within the same instance Enable lane bonding On Off When enabled the PMA uses the same clock...

Page 128: ...hs The CMU PLL has a larger frequency range than the ATX PLL The ATX PLL is designed to improve jitter performance and achieves lower channel to channel skew however it supports a narrower range of data rates and reference clock frequencies Another advantage of the ATX PLL is that it does not use a transceiver channel while the CMU PLL does An informational message displays in the message panel if...

Page 129: ...y clock from the 32 clock and feed this clock back into the tx_coreclkin The rx_clkout frequency generated by the Low Latency PHY is the data rate 32 You must generate a 64 frequency from the recovered clock and feed this back into the rx_coreclkin Table 8 4 Datapath Width Support Part 2 of 2 FPGA Fabric Transceiver Interface Width PCS PMA Interface Width tx_clkout and rx_clkout frequency Standard...

Page 130: ... control On Off This option is turned on by default When On the embedded reset controller initiates the reset sequence when it receives a positive edge on the phy_mgmt_clk_reset input signal For more information about the embedded reset controller refer to the Embedded Reset Controller section in the Transceiver Reset Control in Stratix V Devices in volume 3 of the Stratix V Device Handbook Disabl...

Page 131: ... 0 3 Refer to Table 8 3 on page 8 3 for a detailed explanation of these parameters PLL Type CMU ATX Specifies the PLL type Base data rate 1 Lane rate 2 Lane rate 4 Lane rate Specifies Base data rate Input clock frequency Variable Specifies the frequency of the PLL input reference clock The frequency required is the Base data rate 2 You can use any Input clock frequency that allows the PLLs to gene...

Page 132: ...efault value of an analog parameter is shown in bold type Table 8 7 Transceiver and PLL Assignments for Stratix V Devices Sheet 1 of 2 QSF Assignment Name Pin Planner and Assignment Editor Name Description Options Assign To XCVR_IO_PIN_TERMINATION Transceiver I O Pin Termination Specifies the intended on chip termination value for the specified transceiver pin Use External Resistor if you intend t...

Page 133: ...ing the intended supply voltages for a GXB I O pin If your design uses decision feedback equalization DFE or adaptive equalization AEQ you must set this parameter to 1 0V Otherwise if you do not make this assignment the compiler automatically sets the correct VCCR_GXB and VCCT_GXB voltage depending on the configured data rate as follows Data rate 6 5 Gbps 0_85V Data rate 6 5 Gbps 1_0V 0_85V 1_0V P...

Page 134: ...ntrol is determined by the XCVR_RX_LINEAR_EQUALIZER_SETT ING assignment TRUE FALSE Pin XCVR_RX_EQ_BW_SEL Receiver Equalizer Gain Bandwidth Select Sets the gain peaking frequency for the equalizer For data rates of less than 6 5Gbps set to HALF For higher data rates set to FULL FULL HALF Pin XCVR_RX_SD_ENABLE Receiver Signal Detection Unit Enable Disable Enables or disables the receiver signal dete...

Page 135: ...p Specifies the pre tap pre emphasis setting 0 15 Pin XCVR_TX_RX_DET_ENABLE Transmitter s Receiver Detect Block Enable Enables or disables the receiver detector circuit at the transmitter TRUE FALSE Pin XCVR_TX_RX_DET_MODE Transmitter s Receiver Detect Block Mode Sets the mode for receiver detect block 0 15 Pin XCVR_TX_RX_DET_OUTPUT_SEL Transmitter s Receiver Detect Block QPI PCI Express Control D...

Page 136: ...s with the interface type and places the interface name inside the box The interface type and name are used in the _hw tcl file that describes the component If you turn on Show signals the block diagram displays all top level signal names Figure 8 2 Top Level Low Latency Signals Low Latency PHY IP Core Top Level Signals tx_serial_data n rx_serial_data n rx_is_lockedtodata n 1 0 rx_is_lockedtoref n...

Page 137: ...ass Mode or the MAC in PMA Direct mode must be able to accept data as soon as it comes out of reset tx_clkout n 1 0 Output This is the clock for TX parallel data tx_ready n 1 0 Output When asserted indicates that the Low Latency IP core has exited the reset state is ready to receive data from the MAC This signal is available if you select Enable embedded reset control on the Additional Options tab...

Page 138: ...X CDR is locked to the input reference clock This signal is optional When the RX CDR is locked to data you can ignore transitions on this signal If latency is not critical you can read the value of this signal from the rx_is_lockedtoref register pll_locked n 1 0 Output When asserted indicates that the TX PLL is locked to the input reference clock This signal is asynchronous tx_bitslip n 1 0 Output...

Page 139: ...PCS Dynamic Reconfiguration Native PMA Control Channel Control S Avalon MM Control S Low Latency PHY Controller Tx Data to Embedded Controller to Reconfiguration Controller to MAC Tx Parallel Data Rx Data Rx Parallel Data M Avalon MM PHY Mgmt S Rx Serial Data Tx Serial Data TX PLL CMU n n Table 8 14 Avalon MM PHY Management Interface Part 1 of 2 Signal Name Direction Description phy_mgmt_clk Input...

Page 140: ...lue is all 1s Channel n can be reset when bit n 1 0x042 1 0 W reset_control write Writing a 1 to bit 0 initiates a TX digital reset using the reset controller module The reset affects channels enabled in the reset_ch_bitmask Writing a 1 to bit 1 initiates a RX digital reset of channels enabled in the reset_ch_bitmask R reset_status read Reading bit 0 returns the status of the reset controller TX r...

Page 141: ...iver Reconfiguration Controller Table 8 16 describes the signals in the reconfiguration interface This interface uses a clock provided by the reconfiguration controller Simulation Files and Example Testbench Refer to Running a Simulation Testbench on page 1 4 for a description of the directories and files that the Quartus II software creates automatically when you generate your Low Latency PHY IP ...

Page 142: ...8 18 Chapter 8 Low Latency PHY IP Core Simulation Files and Example Testbench Altera Transceiver PHY IP Core March 2012 Altera Corporation User Guide ...

Page 143: ...terface CPRI Open Base Station Architecture Initiative OBSAI 1588 Ethernet Figure 9 1 illustrates the top level interfaces and modules of the Deterministic Latency PHY IP core As Figure 9 1 the physical coding sublayer PCS includes the following functions TX and RX Phase Compensation FIFO Byte serializer and deserializer 8B 10B encoder and decoder Word aligner TX bit slipper The data that the Dete...

Page 144: ...gotiation When auto negotiation is required the channels initialize at the highest supported frequency and switch to successively lower data rates if frame synchronization is not achieved If your design requires auto negotiation choose a base data rate that minimizes the number of PLLs required to generate the clocks required for data transmission By selecting an appropriate base data rate you can...

Page 145: ...e transceiver block must use a delay estimate FIFO to determine delay estimates and the required phase adjustments Delay Estimation Logic This section provides the equations to calculate delays when the Deterministic Latency PHY IP core implements CPRI protocol CPRI defines the radio base station interface between network radio equipment controllers REC and radio equipment RE components Figure 9 2...

Page 146: ...at RX pins latency time in RE RX latency time in REC Round_trip_latency tx_clkout_period RX_latency in REC rx_clkout_period tPDIO RX_deser rx_clkout_phase_WRT_tx_clkout 360 rx_clkout_period Total Delay Arrival_time Launch_time Total Delay Uncertainty Round trip delay estimates are subject to power voltage and temperature PVT variation tRXCLK_Phase_detector_uncertainty 2 max tGLL_phase_step tCDR_to...

Page 147: ...tera device families Double word with byte serializer 1 0 0 5 0 5 0 2 0 Double word without byte serializer 1 0 1 0 2 0 0 3 0 Table 9 2 TX PCS Total Latency Datapath Attributes TX Phase Comp FIFO Serializer 8B 10B Bitslip Total Clock Cycles Table 9 3 RX PCS Total Latency Datapath Attributes RX Phase Comp FIFO Byte Ordering Deserializer 8B 10B Word Aligner TotalClock Cycles Single word with byte de...

Page 148: ...erface width 8 16 32 Specifies the word size between the FPGA fabric and PCS Refer to Sample Channel WIdth Options for Supported Serial Data Rates on page 9 7 for the data rates supported at each word size PCS PMA interface width 10 20 Specifies the datapath width between the transceiver PCS and PMA A deserializer in the PMA receives serial input data from the RX buffer using the high speed recove...

Page 149: ...t minimizes the number of PLLs required to generate the clocks for data transmission Table 9 1 on page 9 2 lists the recommended Base data rates for various Data rates The available options are dynamically computed based on the Data rate you specified as long as those Base data rates are within the frequency range of the PLL Input clock frequency Data rate 20 Data rate 10 Data rate 8 Data rate 5 D...

Page 150: ...ified word alignment pattern which is currently forced to K28 5 0011111010 is always placed in the least significant byte LSB of a word with a fixed latency of 3 cycles User logic can assume the LSB placement Altera recommends the deterministic latency state machine mode for new designs During the word alignment process the parallel clock shifts the phase to align to the data This phase shifting w...

Page 151: ... the run length which is the maximum legal number of contiguous 0s or 1s This option also creates the rx_rlv output signal which is asserted when a run length violation is detected Run length 5 160 Specifies the threshold for a run length violation Must be a multiple of 5 Create optional word aligner status ports On Off Enable this option to include the rx_patterndetect and rx_syncstatus ports Cre...

Page 152: ... transceiver pin Use External Resistor if you intend to use off chip termination 85_OHMS 100_OHMS 120_OHMS 150_OHMS EXTERNAL_ RESISTOR Pin XCVR_REFCLK_PIN_ TERMINATION Transceiver Dedicated Refclk Pin Termination Specifies the intended termination value for the specified refclk pin DC_COUPLING_ INTERNAL_100 _OHM DC_COUPLING_ EXTERNAL_ RESISTOR AC_COUPLING Pin XCVR_RX_BYPASS_EQ_ STAGES_234 Receiver...

Page 153: ...pecifying the intended supply voltages for a GXB I O pin If your design uses decision feedback equalization DFE or adaptive equalization AEQ you must set this parameter to 1 0V Otherwise if you do not make this assignment the compiler automatically sets the correct VCCR_GXB and VCCT_GXB voltage depending on the configured data rate as follows Data rate 6 5 Gbps 0_85V Data rate 6 5 Gbps 1_0V 0_85V ...

Page 154: ...in control is determined by the XCVR_RX_LINEAR_EQUALIZER_SETT ING assignment TRUE FALSE Pin XCVR_RX_EQ_BW_SEL Receiver Equalizer Gain Bandwidth Select Sets the gain peaking frequency for the equalizer For data rates of less than 6 5Gbps set to HALF For higher data rates set to FULL FULL HALF Pin XCVR_RX_SD_ENABLE Receiver Signal Detection Unit Enable Disable Enables or disables the receiver signal...

Page 155: ...re Tap Specifies the pre tap pre emphasis setting 0 15 Pin XCVR_TX_RX_DET_ENABLE Transmitter s Receiver Detect Block Enable Enables or disables the receiver detector circuit at the transmitter TRUE FALSE Pin XCVR_TX_RX_DET_MODE Transmitter s Receiver Detect Block Mode Sets the mode for receiver detect block 0 15 Pin XCVR_TX_RX_DET_OUTPUT_SEL Transmitter s Receiver Detect Block QPI PCI Express Cont...

Page 156: ... Help f For more information about Quartus II Settings refer to Quartus II Settings File Manual Interfaces This section describes interfaces of the Deterministic Latency Transceiver PHY It includes the following topics Ports Register Interface Dynamic Reconfiguration Ports Figure 9 3 illustrates the top level signals of the Deterministic Latency PHY IP core The variables in Figure 9 3 represent th...

Page 157: ... n w 1 0 rx_clkout n 1 0 rx_datak n w s 1 0 rx_runningdisp n w s 1 0 phy_mgmt_clk phy_mgmt_clk_reset phy_mgmt_address 8 0 phy_mgmt_writedata 31 0 phy_mgmt_readdata 31 0 phy_mgmt_write phy_mgmt_read phy_mgmt_waitrequest pll_ref_clk Deterministic PHY Top Level Signals tx_serial_data n 1 0 rx_serial_data n 1 0 tx_ready rx_ready pll_locked p 1 0 rx_bitslipboundaryselectout n 5 1 0 tx_bitslipboundaryse...

Page 158: ...MAC The ready latency on this interface is 0 so that the PHY must be able to accept data as soon as it comes out of reset tx_clkout n 1 0 Output This is the clock for TX parallel data control and status signals tx_datak n d s 1 0 Sink Data and control indicator for the received data When 0 indicates that tx_parallel_data is data when 1 indicates that tx_parallel_data is control Table 9 12 Avalon S...

Page 159: ...ndaryselectout n 5 1 0 Output Specifies the number of bits slipped to achieve word alignment In 3G 10 bit mode the output is the number of bits slipped If no bits were slipped the output is 0 In 6G 20 bit mode the output is 19 the number of bits slipped If no bits were slipped the output is 19 The default value of rx_bitslipboundaryselectout 4 0 before alignment is achieved is 5 b01111 in 3G mode ...

Page 160: ..._patterndetect n d s 1 0 Output When asserted indicates that the programmed word alignment pattern has been detected in the current word boundary rx_rlv n 1 0 Output When asserted indicates a run length violation Asserted if the number of consecutive 1s or 0s exceeds the number specified using the parameter editor Table 9 15 Serial Interface and Status Signals Part 2 of 2 1 Signal Name Direction S...

Page 161: ... Parallel Data Rx Data Rx Parallel Data M Avalon MM PHY Mgmt S Rx Serial Data Status Reconfig to and from Transceiver Tx Serial Data Table 9 17 Avalon MM PHY Management Interface Part 1 of 2 Signal Name Direction Description phy_mgmt_clk Input Avalon MM clock input There is no frequency restriction for Stratix V devices however if you plan to use the same clock for the PHY management interface and...

Page 162: ...Y IP Core Registers Part 1 of 3 Word Addr Bits R W Register Name Description PMA Common Control and Status Registers 0x021 31 0 RW cal_blk_powerdown Writing a 1 to channel n powers down the calibration block for channel n 0x022 31 0 R pma_tx_pll_is_locked Bit P indicates that the TX CMU PLL P is locked to the input reference clock There is typically one pma_tx_pll_is_locked bit per system Reset Co...

Page 163: ...61 31 0 RW phy_serial_loopback Writing a 1 to channel n puts channel n in serial loopback mode For information about pre or post CDRserial loopback modes refer to Loopback Modes on page 10 39 0x064 31 0 RW pma_rx_set_locktodata When set programs the RX CDR PLL to lock to the incoming data Bit n corresponds to channel n 0x065 31 0 RW pma_rx_set_locktoref When set programs the RX CDR PLL to lock to ...

Page 164: ...tx_control Reserved 5 1 RW tx_bitslipboundary_select Sets the number of bits that the TX bit slipper needs to slip To block Word aligner 0 RW tx_invpolarity When set the TX interface inverts the polarity of the TX data To block 8B 10B encoder 0x084 31 1 RW Reserved 0 RW rx_invpolarity When set the RX channels inverts the polarity of the received data To block 8B 10B decoder 0x085 31 4 RW pcs8g_rx_...

Page 165: ...Placement and Utilization The Deterministic Latency PHY IP core has the following restriction on channel placement Channels 0 2 in transceiver banks GXB_L0 and GSB_R0 of Arria V devices are not available for deterministic latency protocols Example 9 1 Informational Messages for the Transceiver Reconfiguration Interface PHY IP will require 2 reconfiguration interfaces for connection to the external...

Page 166: ...stic Latency PHY IP core This chapter provides additional information about the document and Altera Figure 9 5 Channel Placement and Available Channels in Arria V Devices GXB_R0 GXB_R1 GXB_L0 GXB_L1 GXB_R2 GXB_L2 Devices Available Number of Channels Per Bank Transceiver Bank Names 5AGXB5KF40 5AGXB7KF40 5AGXA5HF35 5AGXA7HF35 5AGXB1HF35 5AGXB1HF40 5AGXB3HF35 5AGXB3HF40 5AGXB5HF35 5AGXB7HF35 5AGXA1EF...

Page 167: ...configure a channel to support Ethernet running at 1 Gbps or 10 Gbps You can also change the width of the datapath The Transceiver Reconfiguration Controller provides access to the following settings Transceiver calibration functions ATX PLL calibration PMA analog controls Adaptive equalization AEQ The Transceiver Reconfiguration Controller also provides access to the following channel and TX PLL ...

Page 168: ...page 10 4 Performance and Resource Utilization on page 10 5 Parameter Settings on page 10 5 Interfaces on page 10 7 Reconfiguration Controller Memory Map on page 10 9 PMA Analog Controls on page 10 11 EyeQ on page 10 12 DFE on page 10 14 AEQ on page 10 16 ATX PLL Calibration on page 10 17 PLL Reconfiguration on page 10 18 Channel and PLL Reconfiguration on page 10 21 Streamer Module on page 10 22 ...

Page 169: ...ent interface You initiate reconfiguration using a series of Avalon MM reads and writes to the appropriate registers of the Transceiver Reconfiguration Controller The Transceiver Reconfiguration Controller translates the device independent commands received on the reconfiguration management interface to device dependent commands on the transceiver reconfiguration interface For more information ref...

Page 170: ...ct write mode you perform Avalon MM reads and writes to initiate a reconfiguration of the PHY IP For more information refer to Direct Write Reconfiguration on page 10 29 Table 10 1 shows the features that you can reconfigure or control using register based and MIF based access modes Device Family Support IP cores provide either final or preliminary support for target Altera device families These t...

Page 171: ...Interfaces Transceiver PHY Transceiver Reconfiguration Controller v11 1 To configure the Transceiver Reconfiguration Controller in Qsys in the Component Library type Transc in the Search Box Qsys filters all available components for this text string and displays the Transceiver Reconfiguration Controller which is in the Interface Protocols Transceiver PHY category Table 10 3 Resource Utilization C...

Page 172: ...cal Channel Numbering on page 10 31 for more information about grouping interfaces Transceiver Calibration Functions Enable offset cancellation On When enabled the Transceiver Reconfiguration Controller includes the offset cancellation functionality This option is always on Offset cancellation occurs automatically at power up and runs only once Enable duty cycle calibration On Off When enabled thi...

Page 173: ...amic reconfiguration interface The Transceiver Reconfiguration Controller communicates with the PHY IP cores using this interface Figure 10 2 Top Level Signals of the Transceiver Reconfiguration Controller Transceiver Reconfiguration Controller Top Level Signals Reconfiguration Management Avalon MM Slave Interface MIF Reconfiguration Avalon MM Master Interface Transceiver Reconfiguration reconfig_...

Page 174: ... from the Transceiver Reconfiguration Controller to the PHY IP core reconfig_from_xcvr n 46 1 0 1 Input Parallel reconfiguration bus from the PHY IP core to the Transceiver Reconfiguration Controller reconfig_busy Output When asserted indicates that a reconfiguration operation is in progress and no further reconfiguration operations should be performed You can monitor this signal to determine the ...

Page 175: ...integrity modules It provides links to the sections describing the registers in each module Figure 10 3 Memory Map of the Transceiver Reconfiguration Controller Registers Direct Addressing Address Offset 0x00 0x13 0x0B 0x1B 0x2B 0x33 0x3B 0x43 0x7F Transceiver Reconfiguration Controller Avalon MM Interface reconfig_mgmt_ Avalon MM Registers Signal Integrity Features DFE ADCE ATX Tuning MIF Streame...

Page 176: ... are unavailable while this function is running 1 If you select a TX only transceiver PHY duty cycle calibration does not run To run duty cycle calibration you can instantiate an unused receiver channel Auxiliary Transmit ATX PLL Calibration ATX calibration tunes the parameters of the ATX PLL for optimal performance This function runs once after power up You can rerun this function by writing into...

Page 177: ...ynamic updates The Transceiver Reconfiguration Controller maps the logical address to the physical address 7 h09 9 0 R physical channel address The physical channel address The Transceiver Reconfiguration Controller maps the logical address to the physical address 7 h0A 9 R control and status Error When asserted indicates an error This bit is asserted if any of the following conditions occur The c...

Page 178: ... tool that analyzes the incoming data including the receiver s gain noise level and jitter after the receive buffer Table 10 10 PMA Offsets and Values Offset Bits R W Register Name Description 0x0 6 0 RW VOD VOD The following encodings are defined 6 b000000 6 b111111 0 63 0x1 5 0 RW Pre emphasis pre tap The following encodings are defined 5 b00000 5 b10000 0 5 b00001 5 b01111 15 to 1 5 b10001 5b 1...

Page 179: ...elds valid data the width of the eye is equal to 0 which means the eye is closed Table 10 11 lists the memory mapped EyeQ registers that you can access using Avalon MM reads and writes on reconfiguration management interface 1 All undefined register bits are reserved Table 10 11 Eye Monitor Registers Recon fig Addr Bits R W Register Name Description 7 h10 9 0 RW logical channel number The logical ...

Page 180: ...oring the BER of the received data at each setting and specify the DFE settings that yield the widest eye Table 10 13 lists the direct DFE registers that you can access using Avalon MM reads and writes on reconfiguration management interface 1 All undefined register bits are reserved Table 10 12 EyeQ Offsets and Values Offset Bits R W Register Name Description 0x0 1 RW Control Writing a 1 to this ...

Page 181: ... Bits R W Register Name Description Table 10 14 DFE Offset and Values Part 1 of 2 Offset Bits R W Register Name Description 0x0 1 RW power on A 0 to 1 transition on this bit triggers DFE calibration 0 RW adaptation engine enable Writing a 1 triggers the adaptive equalization engine 0x1 3 0 RW tap 1 Specifies the coefficient for the first post tap The valid range is 0 15 0x2 3 RW tap 2 polarity Spe...

Page 182: ...ity of the fifth post tap as follows 0 negative polarity 1 positive polarity 2 0 RW tap 5 Specifies the coefficient for the fifth post tap The valid range is 0 7 0x6 2 0 RW reference voltage level Specifies the reference voltage The following encodings are defined 3 b000 0 mV 3 b001 35 mV 3 b010 55 mV 3 b011 70 mV 3 b100 110 mV 3 b101 150 mV 3 b110 200 mV 3 b111 1000 mV Table 10 14 DFE Offset and ...

Page 183: ... Read Writing a 1 to this bit triggers a read operation 0 W Write Writing a 1 to this bit triggers a write operation 7 h2B 3 0 RW aeq_offset Specifies the address of the AEQ register to be read or written Refer to Table 10 16 for details 7 h2C 15 0 RW data Specifies the read or write data Table 10 15 AEQ Registers Part 2 of 2 Recon fig Addr Bits R W Register Name Description Table 10 16 AEQ Offset...

Page 184: ...cal channel number The logical channel number The Transceiver Reconfiguration Controller maps the logical address to the physical address 7 h32 9 R control and status Error When asserted indicates an invalid channel or address This bit is asserted after a write operation if the selected logical channel number selects a logical channel interface that is not connected to an ATX PLL It is also be ass...

Page 185: ... instantiates at power up Figure 10 4 illustrates these parameters 1 You must provide your own custom reset controller if you dynamically reconfigure the PLLs in your design For more information on the Stratix V reset sequence refer to Transceiver Reset Control in Stratix V Devices in volume 3 of the Stratix V Device Handbook When you specify multiple PLLs you must use the QSF assignment XCVR_TX_P...

Page 186: ...hysical address 7 h41 9 0 R physical channel address The physical channel address The Transceiver Reconfiguration Controller maps the logical address to the physical address 7 h42 9 R control and status When asserted indicates an error This bit is asserted if any of the following conditions occur The channel address is invalid The PHY address is invalid The address offset is invalid 8 R MIF Busy W...

Page 187: ...troller GUI you can change the following channel settings TX PMA settings RX PMA settings RX CDR input clock Table 10 20 PLL Reconfiguration Offsets and Values Offset Bits R W Name Description 0x0 2 0 RW logical refclk selection When written initiates reference clock change to the logical reference clock indexed by bits 2 0 For the Custom and Low Latency PHY IP cores this index refers to the Numbe...

Page 188: ...able PLL reconfiguration support block in the Transceiver Reconfiguration Controller GUI you can change the following channel settings TX PLL settings TX PLL selection 1 When you specify multiple PLLs you must use the QSF assignment XCVR_TX_PLL_RECONFIG_GROUP to identify the PLLs within a reconfiguration group The XCVR_TX_PLL_RECONFIG_GROUP assignment identifies PLLs that the Quartus II Fitter can...

Page 189: ...ransfers a mif file which contains the reconfiguration data 2 b01 Direct Write In this mode you specify a logical channel a register offset and data Depending on the logical channel specified the Transceiver Reconfiguration Controller may mask some of the data specified to prevent read only values that were optimized during startup from being over written In particular this mode protects the follo...

Page 190: ...econfiguration on page 10 28 for an example of a MIF update Table 10 23 Streamer Module Internal MIF Register Offsets Offset Bits R W Register Name Description 0x0 31 0 RW MIF base address Specifies the MIF base address 0x1 2 RW Clear error status Writing a 1 to this bit clears any error currently recorded in an indirect register This register self clears Any error detected in the error registers ...

Page 191: ... design with two channels This design example includes two transceiver PHY IP core instances running at different data rates Both transceiver PHY IP core instances have two TX PLLs specified to support both 1 Gbps and 2 5 Gbps data rates The Quartus II software generates two TX PLL mif files for each PLL The difference between the mif files is the PLL reference clock specified To dynamically recon...

Page 192: ...x V MIF format Entries 3 7 and n are data records Table 10 24 Opcodes for MIF Files Opcode Opcode Description 5 b00000 Reserved 5 b00001 Start of MIF 5 b00010 Channel format indicator specifying the MIF channel type The following encodings are defined 2 b00 Duplex channel 2 b01 TX PLL CMU 2 b10 RX only channel 2 b11 TX only channel 5 b00011 CDR Input Clock switch 5 b00100 PLL switch 5 b00101 5 b11...

Page 193: ...r 2 Write the logical channel number of the channel to be updated to the logical channel number register 3 Write the feature offset address 4 Write the appropriate data value to the data register 5 Write the control and status register write bit to 1 b1 6 Read the control and status register busy bit Continue to read the busy bit while its value is one 7 When busy 0 the Transceiver Reconfiguration...

Page 194: ...setting by streaming the contents of a MIF file through the Streamer Module 1 Write the logical channel number to the Streamer logical channel register 2 Write MIF mode 2 b00 to the Streamer control and status register mode bits 3 Write the MIF base address 0x0 to the Streamer offset register 4 Write the base address of the MIF file to the Streamer data register 5 Write the Streamer control and st...

Page 195: ...ate a write of all the data set in the previous steps 6 Repeat steps 3 through 5 if the offset data length is greater than 1 Increment the offset value by 1 for each additional data record 7 Read the control and status register busy bit When the busy bit is deasserted the operation has completed Example 10 4 Reconfiguration of Logical Channel 0 Using A MIF Setting logical channel 0 write_32 0x38 0...

Page 196: ...writes this data to logical channel 0 Figure 10 6 Sample MIF Example 10 5 Streamer Mode 1 Reconfiguration Setting logical channel 0 write_32 0x38 0x0 Setting Streamer to mode to 1 write_32 0x3A 4 b0100 Setting Streamer offset register to the offset address In the example record the first offset address is 0x0 write_32 0x3B 0x0 Setting data register with the first data record write_32 0x3C 16 b0010...

Page 197: ... Transceiver Reconfiguration Controller and a transceiver bank after running the Quartus II Fitter The transceiver PHY IP cores create a separate reconfiguration interface for each channel and each TX PLL Each transceiver PHY IP core reports the number of reconfiguration interfaces it requires in the message pane of its GUI You must take note of this number so that you can enter it as a parameter ...

Page 198: ...ion User Guide Figure 10 8 shows the Low Latency PHY IP core GUI specifying 32 channels The message pane indicates that reconfiguration interfaces 0 31 are for the transceiver channels and reconfiguration interfaces 32 63 are for the TX PLLs 1 After Quartus II compilation many of the interfaces are merged Figure 10 8 Low Latency Transceiver PHY Example ...

Page 199: ...ces each with four channels For this design you would enter 16 for the Number of reconfiguration interfaces and 8 8 for the Optional interface grouping parameter Depending upon the transceiver PHY IP core and the parameters specified the number of reconfiguration interfaces varies For a single channel RX only transceiver instance there is a single reconfiguration interface For example one reconfig...

Page 200: ...hannels When two transceiver PHY instances each with four bonded channels are connected to a Transceiver Reconfiguration Controller the reconfiguration buses of the two instances are concatenated Figure 10 10 and Table 10 25 show the order and numbering of reconfiguration interfaces The Quartus II software assigns the data channels logical channel numbers 0 to 3 for each transceiver PHY instance T...

Page 201: ...l address 9 accesses the TX PLL for data channel 1 and so on In simulation to reconfigure the TX PLL for channel 0 specify logical address 8 in the Streamer module s logical channel number The Streamer module maps the logical channel to the physical channel which would be the same value for all eight channels Table 10 25 Channel Ordering for Concatenated Transceiver Instances Logical Interface Num...

Page 202: ...nels do not share TX PLLs For each transceiver PHY IP core instance the Quartus II software assigns the data channels sequentially beginning at logical address 0 and assigns the TX PLLs the subsequent logical addresses Table 10 28 illustrates the logical channel numbering for two transceiver PHY IP cores one with 4 channels and one with 2 channels Table 10 27 Post Fit Logical Channel Numbers for E...

Page 203: ...s incorrect connections between two Transceiver Reconfiguration Controllers and six transceiver channels Two Transceiver Reconfiguration Controllers cannot access a single reconfiguration interface because there is no arbitration logic to prevent concurrent access The configuration shown in Figure 10 12 results in a Quartus II compilation error Figure 10 11 Correct Connections Figure 10 12 Incorre...

Page 204: ...he PLLs connect to the same reference clock The PLLs connect to the same Transceiver Reconfiguration Controller Figure 10 13 illustrates a design where the CMU PLL in channel 1 provides the clock to three Custom PHY channels and two 10GBASE R PHY channels Figure 10 13 PLL Shared by Multiple Transceiver PHY IP Cores in a Single Transceiver Bank Transceiver Bank to Embedded Processor Reconfig to and...

Page 205: ...fer is active Figure 10 14 illustrates these modes In addition to the pre CDR and post CDR loopback modes available in the Transceiver Reconfiguration Controller register map all the of PHYs with the exception of PCI Express support serial loopback mode in both Stratix IV and Stratix V devices This mode is enabled by writing the phy_serial_loopback register 0x061 using the Avalon MM PHY management...

Page 206: ...ing the RX buffer The received data is available to the FPGA logic for verification Using the serial loopback option you can check the operation of all enabled PCS and PMA functional blocks in the TX and RX channels When serial loopback is enabled the TX channel sends the data to both the tx_serial_data output port and the RX channel Figure 10 15 Serial Loopback Tx PCS Rx PCS FPGA Fabric Tx PMA tx...

Page 207: ...dent In general reconfiguration logic is integrated with the transceiver channels for simple configurations and is separately instantiated for more complex designs that use a large number of channels or instantiate more than one protocol in a single transceiver quad For Stratix V devices transceiver dynamic reconfiguration is always performed using the separately instantiated Transceiver Reconfigu...

Page 208: ...d write registers and memory and test bus signals When you instantiate a transceiver PHY in a Stratix V device the transceiver PHY IP core provides informational messages specifying the number of required reconfiguration interfaces in the message pane as Example 11 1 illustrates Although you must initially create a separate reconfiguration interface for each channel and TX PLL in your design when ...

Page 209: ...erences between the parameters and signals for the XAUI PHY IP core and the ALTGX megafunction when configured in the XAUI functional mode Parameter Differences Table 11 2 lists the XAUI PHY parameters and the corresponding ALTGX megafunction parameters Table 11 2 Comparison of ALTGX Megafunction and XAUI PHY Parameters Part 1 of 2 ALTGX Parameter Name Default Value XAUI PHY Parameter Name Comment...

Page 210: ...eemphasis 1st post tap 0 Preemphasis pre tap setting 0 Preemphasis second post tap setting 0 Analog controls Off Enable ADCE Off Not available as parameters in the MegaWizard interface Not available in 10 0 Enable channel and transmitter PLL reconfig Off Starting channel number 0 No longer required Automatically set to 0 The Quartus II software handles lane assignments Enable run length violation ...

Page 211: ...phase_comp_fifo_error n 4 1 0 Not available cal_blk_powerdown Not available rx_syncstatus 2 n 1 0 rx_syncstatus n 2 1 0 rx_patterndetect 2 n 1 0 Not available rx_invpolarity n 1 0 Not available rx_ctrldetect 2 n 1 0 Not available rx_errdetect 2 n 1 0 rx_errdetect n 2 1 0 rx_disperr 2 n 1 0 rx_disperr n 2 1 0 tx_invpolarity n 1 0 Not available rx_runningdisp 2 n 1 0 Not available rx_rmfifofull 2 n ...

Page 212: ...deserialization factor from the pin to the FPGA fabric Table 11 3 Correspondences between XAUI PHY Stratix IV GX and Stratix V Device Signals Part 3 of 3 1 Stratix IV GX Devices Stratix V Devices Signal Name Width Signal Name Width Table 11 4 Comparison of ALTGX Megafunction and PHY IP Core for PCI Express PHY PIPE Parameters Part 1 of 2 ALTGX Parameter Name Default Value PCI Express PHY PIPE Para...

Page 213: ...l detection Off Signal Detect threshold 4 Use external receiver termination Off RX term 100 Transmitter buffer power VCCH 1 5 TX Vcm 0 65 Use external transmitter termination Off TX Rterm 100 VCO control setting 5 Pre emphasis 1st post tap 18 Not available in MegaWizard Interface Use assignment editor to make these assignments Pre tap 0 2nd post tap 0 DPRIO VOD Pre em Eq and EyeQ Off DPRIO Channel...

Page 214: ...x_forceelecidle pipe_txelecidle n 1 0 txswing pipe_txswing n 1 0 tx_pipedeemph 0 pipe_txdeemph n 1 0 tx_pipemargin 2 0 pipe_txmargin 3 n 1 0 rateswitch 0 pipe_rate 1 0 n 1 0 powerdn pipe_powerdown 2 n 1 0 rx_elecidleinfersel pipe_eidleinfersel 3 n 1 0 rx_dataout pipe_rxdata n d 1 0 rx_ctrldetect pipe_rxdatak d 8 n 1 0 pipedatavalid pipe_rxvalid n 1 0 pipe8b10binvpolarity pipe_rxpolarity n 1 0 pipe...

Page 215: ...rx_rlv n 1 0 rx_datain rx_serial_data n 1 0 tx_dataout tx_serial_data n 1 0 Reconfiguration cal_blk_clk These signals are included in the reconfig_to_xcvr bus 1 reconfig_clk 1 fixedclk 1 reconfig_togxb reconfig_to_xcvr variable reconfig_fromgxb reconfig_from_xcvr variable Avalon MM Management Interface Not available phy_mgmt_clk_reset 1 phy_mgmt_clk 1 phy_mgmt_address 8 0 phy_mgmt_read 1 phy_mgmt_...

Page 216: ... Which subprotocol will you be using 4 8 Not available What is the channel width Serialization factor What is the effective data rate Data rate What is the input clock frequency Input clock frequency tx rx_8b_10b_mode Enable 8B 10B encoder decoder Not available Enable manual disparity control Create optional 8B10B status ports What is the deserializer block width Single Double Deserializer block w...

Page 217: ...t is the byte ordering pattern Byte ordering pattern Note to Table 11 6 1 This parameter is on the Datapath tab Table 11 6 Comparison of ALTGX Megafunction and Custom PHY Parameters Part 2 of 2 Table 11 7 Custom PHY Correspondences between Stratix IV GX Device and Stratix V Device Signals ALTGX Custom PHY Width Avalon MM Management Interface Not available phy_mgmt_clk_reset 1 phy_mgmt_clk 1 phy_mg...

Page 218: ... pll_locked and rx_pll_clocked in Stratix IV Stratix V only has pll_locked rx_clkout These signals are now available as control and status registers Refer to Register Descriptions on page 7 21 rx_phase_comp_fifo_error rx_seriallpbken tx_phase_comp_fifo_error tx_invpolarity Transceiver Reconfiguration reconfig_togxb 3 0 reconfig_to_xcvr variable reconfig_fromgxb 16 0 reconfig_from_xcvr variable Not...

Page 219: ...ER count functionality is for Stratix IV devices only Removed pma_rx_signaldetect register The 10GBASE R PHY does not support this functionality XAUI February 2012 1 5 Removed reset bits at register 0x081 The reset implemented Cat register 0x044 provides more comprehensive functionality Removed pma_rx_signaldetect register The XAUI PHY does not support this functionality PCI Express PIPE February ...

Page 220: ... Changed definition of phy_mgmt_clk_reset This signal is active high and level sensitive Custom December 2011 1 4 Added N and feedback compensation options for bonded clocks Added Enable Channel Interface parameter which is required for dynamic reconfiguration of transceivers Corrected formulas for signal width in top level signals figure Changed definition of phy_mgmt_clk_reset This signal is act...

Page 221: ... Updated directory names in simulation testbench 10GBASE R PHY Transceiver November 2011 1 3 Added support for Stratix V devices Added section discussing transceiver reconfiguration in Stratix V devices Removed rx_oc_busy signal which is included in the reconfiguration bus Updated QSF settings to include text strings used to assign values and location of the assignment which is either a pin or PLL...

Page 222: ... strings used to assign values and location of the assignment which is either a pin or PLL Low Latency PHY November 2011 1 3 Added base data rate lane rate input clock frequency and PLL type parameters Updated QSF settings to include text strings used to assign values and location of the assignment which is either a pin or PLL Revised reset options The 2 options for reset are now the embedded rese...

Page 223: ... IV GX HardCopy IV and Stratix IV GX devices Added register descriptions for the automatic reset controller to the Low Latency PHY IP Core chapter Added two steps to procedure to reconfigure a PMA control in the Transceiver Reconfiguration Controller chapter Corrected RX equalization DC gain in transceiver Reconfiguration Controller chapter It should be 0 4 Corrected serialization factor column in...

Page 224: ...ty 0x088 bits 3 0 Interlaken PHY Transceiver May 2011 1 2 Added details about the 0 ready latency for tx_ready Added PLL support to lane rate parameter description in Table 5 2 on page 5 2 Moved dynamic reconfiguration for the transceiver outside of the Interlaken PHY IP Core The reconfiguration signals now connect to a separate Reconfiguration Controller IP Core Added a reference to PHY IP Design...

Page 225: ...ning how to disable all word alignment functionality Low Latency PHY Transceiver May 2011 1 2 Moved dynamic reconfiguration for the transceiver outside of the Low Latency PHY IP Core The reconfiguration signals now connect to a separate Reconfiguration Controller IP Core Moved dynamics reconfiguration for the transceiver outside of the Custom PHY IP Core The reconfiguration signals now connect to ...

Page 226: ...SOPC Builder Getting Started December 2010 1 1 Removed description of SOPC Builder design flow SOPC Builder is not supported in this release 10GBASE R PHY Transceiver December 2010 1 1 Added Stratix V support Changed phy_mgmt_address from 16 to 9 bits Renamed management interface adding phy_ prefix Renamed block_lock and hi_ber signals rx_block_lock and rx_hi_ber respectively Added top level signa...

Page 227: ...ded support for 8B 10B encoding and decoding in Stratix V devices Added support for rate matching in Stratix V devices Added support for Arria II GX Arria II GZ HardCopy IV GX and Stratix IV GX devices Renamed management interface adding phy_ prefix Changed phy_mgmt_address from 8 to 9 bits Added many optional status ports and renamed some signals Refer to Figure 7 2 on page 7 16 and subsequent si...

Page 228: ... custrain altera com Product literature Website www altera com literature Nontechnical support general Email nacomp altera com software licensing Email authorization altera com Note to Table 1 You can also contact your local Altera sales office or sales representative Visual Cue Meaning Bold Type with Initial Capital Letters Indicate command names dialog box titles dialog box options and other GUI...

Page 229: ...s is important such as the steps listed in a procedure Bullets indicate a list of items when the sequence of the items is not important 1 The hand points to information that requires special attention h The question mark directs you to a software help system with related information f The feet direct you to another document or website with related information m The multimedia icon directs you to a...

Page 230: ...Info 12 Additional InformationAdditional Information Typographic Conventions Altera Transceiver PHY IP Core March 2012 Altera Corporation User Guide ...

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