XRM(2)-DAC-D4/1G User Guide
V2.2 - Mar 8, 2018
3 VHDL Structure
3.1 Introduction
The basic data flow is illustrated in figures 5 and 7 above. The clock components provide a clock for the output
stage at the appropriate rate and the global clock for running the data generation circuitry. Each channel has its
own data generation, DCLK and SYNC generation circuit under control of the host via the local bus interface.
3.2 Major HDL Components
Two top level design files are provided; one for use with ISE (xrm_dac_d4_1g_ise.vhd) and one for use with
Vivado (xrm_dac_d4_1g.vhd). The ISE version includes ports for V4,V5,V6,V7 and K7 designs; unused top-level
ports disappear in ISE during the process of synthesis, place-and-route and bit-file generation. In Vivado, unused
top level ports generate an error. Functionally these are the same although the Vivado version also uses a
wrapper component in order to simplify migration to other interface types ( e.g. AXI). It is anticipated that future
releases of ISE-style code will migrate to using the wrapper component. For the purposes of discussion, both
styles of top-level component are implied by the term 'top level file'
The top level file contains a mixture of sequential statements and component instantiations. These implement
the main blocks of code used in this design:
3.2.1 Clock generation and alignment
The DAC_Clocks component implements the clock generation and alignment code.
Restrictions on the maximum clock rates for the various buffers inside the FPGA require that the OSERDES
output clock must be driven using a BUFR (or a BUFG). This in turn requires selection of the appropriate BUFR
mapping based on the regional clocking capabilities of each FPGA, a function implemented in the dac_ck_map
module.
The BUFRs are instantiated in the dac_ck_ip modules; there are three of these, one for each of the possible
regional clock inputs available. The circuitry to generate the global clock is also contained in this module, with the
generic parameter USE_AS_REF set TRUE on a single instance to instantiate a single instance of the global
clock circuitry module, ck_align.vhd.
For Virtex4 and Virtex5 designs only, the ck_align module uses the dcm_align.vhd, ps_adj.vhd and align_test.vhd
components plus it instantiates the DCMs appropriate to the FPGA being used. These three components
implement the following tasks;
a)
Sampling the input clock signal and generating a pass/fail flag with regard to the alignment of the global
clock with the input clock (align_test.vhd).
b)
Control of the phase setting of the DCM (ps_adj.vhd).
c)
State machine to generate the handshake signals to the host, phase shift and alignment test modules,
determine the optimum phase settings accordingly and then to apply this setting to align the clock
(dcm_align.vhd).
Two DCMs must be used in each design, since the range of clock frequencies required spans the limits of the LF
and HF modes of DCM operation. These operate with a pre-scaling divide by 2 counter to ensure that clocks are
within the valid ranges for all speed grades of Virtex 4 and Virtex5. The appropriate DCM (LF/HF) is enabled by
the application software, based on the clock frequency specified by the user, as part of the set-up sequence of
the clock chain.
3.2.2 Data Generation and Output
The dac_channel.vhd component instantiates the data generation and output circuitry for each channel. All data
Page 18
VHDL Structure
xrm-dac-d4-1g-manual_v2_2.pdf
