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Alpha Data XRM(2)-DAC-D4/1G, User Manual

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XRM(2)-DAC-D4/1G User Guide
V2.2 - Mar 8, 2018

2 Hardware

2.1 Hardware Operation

The application  must first configure the FPGA with the bit stream using the standard functions provided in the

SDK before any hardware or FPGA registers can be accessed via the local bus .

The various system blocks must be configured in the correct sequence in order to generate analogue signals

correctly.  First the clock source must be established, the synthesiser configured, then the FPGA clock

generation circuitry. Once a stable DCLK signal has been established, the DAC internal registers can be

configured to suit the operating frequency required.

Default register settings are written to the DAC and synthesiser following system reset/ FPGA configuration, but

the stability of the clocks during this period cannot be guaranteed so the full clock configuration sequence should

be explicitly run by the application prior to use.

The DAC initialisation sequence, which must be run for any change in clock frequency requiring alteration of the

control bits for the DAC DLL, defaults to the sequence for the DAC5681. This can be easily changed in the VHDL

to default to the DAC5682Z sequence.  In both cases the assumed DAC clock frequency is 1GHz. Any change in

the clock speed from this value is used to re-configure the clock multiplexing, the settings for the DCM  clock

used  by the FPGA and the DAC registers. This application also provides code to interrogate the DAC type and

implement the correct settings.

As shown in the Block Diagram,  the DAC sample clock fed to DAC I and DAC Q run at the full rate (1GHz

maximum); the relevant DCLK clocks are at half this rate, since the data interface is DDR. A total of four

differential clock ports are available to capture the data clock reference. In practice, only three are used since the

pinout of the FPGA  requires a maximum of three clock regions in order to support the range of Virtex 4 and

Virtex 5 boards. The fourth is connected to a counter for diagnostic purposes.

2.2 Connector Signals

There are five external connectors accessible on the D4-1G board  plus a further two which are used for fast

signalling. Of these, only the TRIG and AUX ports have any significant protection whilst the clock input has

limited overdrive protection.

The DAC outputs are ac coupled and present a 50R output impedance, both of which factors give some limited

protection.

The two UFL connectors used for fast signalling are connected directly to FPGA pins. Any signals outwith normal

2v5 LVCMOS signalling levels may cause permanent damage to the FPGA.

2.3 DAC Serial Interface

The reset state of the DAC configures the serial interface for 3-wire operation. The example code uses a 4-wire

interface so the first operation following a hardware reset of the DAC ( via the RESETB pin of the DAC)  must be

a write to DAC register CONFIG5 which sets D7 to ensure that the DAC is set to operate in 4-wire mode.

The Status and Func ports have no function on the DAC interface.

The maximum speed of the serial interface is 10 MHz (100 ns). The example code runs the state machine at

LCLK/10, controlled by the END_CNT generic. This results in the interface clock running at LCLK/20, limiting the

interface to less than 4 MHz for all settings of LCLK. The default rate is 1.6 MHz  for LCLK= 33 MHz (virtex4,

Virtex 5) or LCLK=80 MHz (Virtex6, Virtex 7, Kintex 7).

Page 9

Hardware
xrm-dac-d4-1g-manual_v2_2.pdf

Summary of Contents for XRM(2)-DAC-D4/1G

Page 1: ...XRM 2 DAC D4 1G User Guide Document Revision 2 2 Mar 8 2018 ...

Page 2: ...e or form without prior written consent from Alpha Data Parallel Systems Ltd Head Office Address 4 West Silvermills Lane Edinburgh EH3 5BD UK Telephone 44 131 558 2600 Fax 44 131 558 2700 email sales alpha data com website http www alpha data com US Office 611 Corporate Circle Suite H Golden CO 80401 303 954 8768 866 820 9956 toll free sales alpha data com http www alpha data com All trademarks ar...

Page 3: ...tion 12 2 11 Clocking on Virtex4 Virtex5 12 2 11 1 Low Frequency Operation 13 2 12 Clocking on Virtex6 Kintex7 and Virtex7 14 2 13 Data Generation 15 2 14 Performance 15 2 15 Board Layout 16 3 VHDL Structure 18 3 1 Introduction 18 3 2 Major HDL Components 18 3 2 1 Clock generation and alignment 18 3 2 2 Data Generation and Output 18 3 2 3 Local bus interface 19 3 2 3 1 Virtex4 Virtex5 19 3 2 3 2 V...

Page 4: ... 19 IPATTERN_REG2 0x12 64 4 20 QPATTERN_REG2 0x13 66 4 21 MEAS0_VAL_REG 0x14 68 4 22 MEAS1_VAL_REG 0x15 70 4 23 MEAS2_VAL_REG 0x16 72 4 24 FREERUN_CNT_REG 0x17 74 4 25 I_ARBWRITE_REG 0x18 76 4 26 Q_ARBWRITE_REG 0x19 78 4 27 ARB _CNTRL_REG 0x1A 80 4 28 ARB _TICK_REG 0x1B 82 4 29 AUXCNTRL_REG 0x1E 84 4 30 PHASE_VALUE_REG 0x1F 86 List of Tables Table 1 SMA and UFL Connectors 17 Table 2 Clock Muxing D...

Page 5: ...quency clocks required for the FPGA must be synthesised in the FPGA fabric using MMCM or DCM These XRM modules are compatible with Alpha Data s family of FPGA cards fitted with Virtex 4 Virtex 5 Virtex 6 Kintex 7 and Virtex 7 devices Both configurations are referred to in this document by the generic title XRM 2 DAC D4 1G where required any DAC specific differences will be made explicit The code a...

Page 6: ...ivisions of 1GHz A pair of LVTTL outputs TRIG and AUX is provided 3V3 signal levels via SMA connectors In addition two direct connections to FPGA pins via UFL connectors are also available for fast signalling interconnect between multiple DAC cards or other devices Page 2 Introduction xrm dac d4 1g manual_v2_2 pdf ...

Page 7: ...XRM 2 DAC D4 1G User Guide V2 2 Mar 8 2018 Figure 1 Block Diagram Page 3 Introduction xrm dac d4 1g manual_v2_2 pdf ...

Page 8: ...n this document refer to release 5 0 of the xrm_dac_d4_1g code dated 15 11 17 Current board hardware revision is rev 6 and this code supports rev 3 and later builds Contact the factory for support for board versions earlier than rev 3 1 4 Alpha Data SDK Versions All VHDL code for legacy boards is built using Alpha Data s SDK version 4 9 3 This SDK version is frozen at this revision All VHDL code f...

Page 9: ...XRM 2 DAC D4 1G User Guide V2 2 Mar 8 2018 project highlighted Figure 2 Default Project Structure Page 5 Introduction xrm dac d4 1g manual_v2_2 pdf ...

Page 10: ...ration of project files for Vivado uses scripts based on those in the Vivado examples provided by the SDK The TCL files automate the generation of Vivado project s which ensures that the xpr files produced include all settings required for correct configuration of both synthesis and post synthesis file generation Specifying these options manually is unlikely to set all options correctly so it is s...

Page 11: ...ts command line parameters to allow projects for single boards single board types or all supported boards to be generated The absence of any command line parameters is interpreted as a command to make all projects Using the batch file allows parameters to be passed to the script something that is not possible when using the standard TCL source command from within Vivado or other TCL interpreters T...

Page 12: ...ed to retain the folder structure shown in the main Vivado folder in order to ensure that TCL files provided work correctly Alterations to this structure will entail the need for extensive modification of paths files embedded in the scripts Page 8 Introduction xrm dac d4 1g manual_v2_2 pdf ...

Page 13: ... the relevant DCLK clocks are at half this rate since the data interface is DDR A total of four differential clock ports are available to capture the data clock reference In practice only three are used since the pinout of the FPGA requires a maximum of three clock regions in order to support the range of Virtex 4 and Virtex 5 boards The fourth is connected to a counter for diagnostic purposes 2 2...

Page 14: ...lt which must be removed in order to program the synthesiser For this reason this port is normally pulled high and should default high at FPGA reset if used in an application otherwise the default configuration data will be ignored by the device 2 6 Synthesiser Programming The synthesiser AD9510 provides three main functions a Clock synthesis b Clock routeing and division c Clock output type The o...

Page 15: ...CCLK cycles so completes in 1ms for a 1GHz clock frequency Pass fail flags can be interrogated via the serial interface 2 8 DAC DLL Control The DAC uses a DLL to align its input registers with DCLK and hence with the data Any change in the DAC clock frequency thus DCLK and FABRCLK requires the DLL control bits in DAC register CONFIG10 to be set appropriately and the DLL re aligned This in turn req...

Page 16: ...DCLK SYNC and data must be produced synchronously for the DAC At maximum speed the data rate required is 500 MHz DDR This is possible by using the 4 1 OSERDES components on Virtex4 and Virtex5 FPGAs On the XRC cards using Virtex4 and Virtex5 FPGAs only regional clock inputs are available to XMC modules so global clocks must be generated using these inputs since the data input pins typically span m...

Page 17: ...from Clocktest for the full range of phase shifts determines the optimum setting and then implements this phase offset using PhaseAdjust Once completed AlignControl signals back to the user application the result of the alignment operation This scheme also ensures that all clocks are constrained within the limits imposed by the various components in the FPGA for all speed grades of the FPGA The DC...

Page 18: ...z Clearly there is some overlap in the clock speed ranges which these two architectures can support which is also dependent on FPGA speed the user should choose the one best suited to the application Code for this style of operation is not included in the example code On Virtex6 and later boards this restriction does not apply as there is no MMCM used 2 12 Clocking on Virtex6 Kintex7 and Virtex7 O...

Page 19: ...ve data samples on each FABRCLK clock cycle In the example code this is implemented by instantiating four identical data sources for each type of waveform produced each offset by the appropriate amount in order to provide the correct signal for each time slot 2 14 Performance Typical performance when producing a 125 MHz sine wave using the internal 1GHz clock is shown below Note that the figure sh...

Page 20: ...XRM 2 DAC D4 1G User Guide V2 2 Mar 8 2018 2 15 Board Layout Figure 8 XRM 2 DAC D4 1G Layout Page 16 Hardware xrm dac d4 1g manual_v2_2 pdf ...

Page 21: ...3 LVTTL J6 General Purpose Fast I O p side FPGA I O bank voltage J7 General Purpose Fast I O n side FPGA I O bank voltage Table 1 SMA and UFL Connectors Note that J6 and J7 connect directly to the FPGA pins and so use the same signalling voltage as the FPGA bank 1 8 volts or 2 5 volts Extreme caution should be used when employing these connectors to avoid damage to the FPGA Page 17 Hardware xrm da...

Page 22: ... the appropriate BUFR mapping based on the regional clocking capabilities of each FPGA a function implemented in the dac_ck_map module The BUFRs are instantiated in the dac_ck_ip modules there are three of these one for each of the possible regional clock inputs available The circuitry to generate the global clock is also contained in this module with the generic parameter USE_AS_REF set TRUE on a...

Page 23: ...Virtex6 Virtex7 Kintex7 Virtex6 Virtex7 Kintex7 boards use a serial bus based OCP interface for communications with the host via the bridge The ocpbus_if vhd component is a wrapper for adb3_ocp_simple_bus_if vhd and the associated files from the SDK This isolates the main XRM code from any SDK modifications by preserving a standard interface This component also supplies the clock interfaces for th...

Page 24: ...tate of the signal at the FPGA pins being read back in the same way as other signals These can also be configured to be used as a single differential signal input output if required Suitable cableforms can be obtained from Samtec or Hirose director from a number of distributors e g Farnell 168 8079 168 8067 3 2 7 Host Access via Local Bus Data register addresses are defined in xrm_dac_d4_1g_pkg vh...

Page 25: ...Kintex7 All registers are 32 bits wide but are 128 bit aligned so addresses A1 to A3 inclusive are unused and register addresses within each page are decoded using local address bits 11 to 4 The OCPBUS_IF component encapsulates the ADB3_OCP_SIMPLE_BUS_IF component which generates the interface and timing signals required for correct operation in the same manner as PLXDSSM above Page 21 VHDL Struct...

Page 26: ... is used to select betwen the pattern test data sequence and the fixeed sine as the test waveform see below In normal operation the waveform output is selected from one of sine DDS generated ramp triangle pulse square or the arbitrary waveform with the DDS sine being the default Figure 9 Waveform Selection Diagram The four waveform selection bits for each channel are located in the control registe...

Page 27: ...lised frequency according to the value Inc 2 16 Fnorm since the DAC is a 16 bit device Four ramp accumulators are used in parallel with each accumulator incremented by 4 Inc and each offset from the preceding one by Inc in the same manner as ther sine wave generation Data simply rolls over so non integer divisions of 2 16 will produce ramps with different starting points but the same slope on each...

Page 28: ...ARB memory but each write completes within the access time of the host doing the write thus eliminating any need for handshaking during this process The write address is auto incremented by each write to the ARB the initial sample is written at address zero the write address is reset to zero when the FPGA generator reset bit is pulsed high The length of the ARB sequence 4096 samples maximum played...

Page 29: ...t setting the multiplexer bit to select the tick signal as the drive source for the AUX or TRIG signal and also configuring the TRIG and or AUX ports as outputs The ARB tick for the I channel is available on the TRIG port whilst that for the Q channel is available on the AUX port 3 3 6 Self Test Pattern The DAC provides a pattern testing mode where what is received on the data inputs is compared t...

Page 30: ...0X03 Q_DDS_REG 0X04 I_INC_REG 0X05 Q_INC_REG 0X06 SYNTH_CNTRL_REG 0X07 SYNTH_STRB_REG 0X08 IDAC_CNTRL_REG 0X09 IDAC_STRB_REG 0X0A QDAC_CNTRL_REG 0X0B QDAC_STRB_REG 0X0C DEVICE_REG 0X0D I_DDSINIT_REG 0X0E Q_DDSINIT_REG 0X0F IPATTERN_REG 0X10 QPATTERN_REG 0X11 IPATTERN_REG2 0X12 QPATTERN_REG2 0X13 MEAS0_VAL_REG 0X14 MEAS1_VAL_REG 0X15 MEAS2_VAL_REG 0X16 FREERUN_CNT_REG 0X17 I_ARBWRITE_REG 0X18 Q_ARB...

Page 31: ...XRM 2 DAC D4 1G User Guide V2 2 Mar 8 2018 Register Name Address PHASE_REG 0X1F Page 27 Register Description xrm dac d4 1g manual_v2_2 pdf ...

Page 32: ...put 0 default input D18 AUX port output signal D17 TRIG port direction signal 1 output 0 default input D16 TRIG port output signal D15 to D8 D15 Alignment reset signal 1 reset active D14 Q channel FPGA data generator reset 1 reset active D13 I channel FPGA data generator reset 1 reset active D12 QDAC hardware reset 1 reset active D11 IDAC hardware reset 1 reset active D10 Determines DLL bypass bit...

Page 33: ...ll zeroes transmitted by FPGA 1 FPGA generator data transmitted to DAC Clock mux msb Clock mux lsb Synth sample clock Synth reference clock 0 0 Extck input Extck input 0 1 Extck input Internal reference 1 0 Internal VCXO Extck input 1 1 Internal VCXO Internal reference Table 2 Clock Muxing D25 D24 Page 29 Register Description xrm dac d4 1g manual_v2_2 pdf ...

Page 34: ...h following alignment sequence meaningful for V4 D16 Alignment routine busy if high meaningful for V4 D15 to D8 D15 DCM lock flag 1 locked D14 DAC 3V3 regulator monitor bit 1 power good D13 DAC 1V8 regulator monitor bit 1 power good D12 Unused D11 GPIO_N J7 input bit D10 GPIO_P J6 input bit D9 External AUX input signal D8 External TRIG input signal D7 to D0 D7 Q channel signal generator busy 1 bus...

Page 35: ... sequence flag 1 init sequence running D1 I channel DAC serial interface complete flag 1 complete set at end of transfer and cleared by start of next transfer D0 I channel DAC serial interface status 1 transfer in progress Page 31 Register Description xrm dac d4 1g manual_v2_2 pdf ...

Page 36: ...z ref clock detect counter D1 D16 200MHz ref clock detect counter D0 lsb D15 to D8 D15 Test clock input detect counter D3 msb D14 Test clock input detect counter D2 D13 Test clock input detect counter D1 D12 Test clock input detect counter D0 lsb D11 Clock input Z detect counter D3 msb D10 Clock input Z detect counter D2 D9 Clock input Z detect counter D1 D8 Clock input Z detect counter D0 lsb D7 ...

Page 37: ... D4 1G User Guide V2 2 Mar 8 2018 D7 to D0 D2 Clock input X detect counter D2 D1 Clock input X detect counter D1 D0 Clock input X detect counter D0 lsb Page 33 Register Description xrm dac d4 1g manual_v2_2 pdf ...

Page 38: ...29 DDS phase increment D29 D28 DDS phase increment D28 D27 DDS phase increment D27 D26 DDS phase increment D26 D25 DDS phase increment D25 D24 DDS phase increment D24 D23 to D16 D23 DDS phase increment D23 D22 DDS phase increment D22 D21 DDS phase increment D21 D20 DDS phase increment D20 D19 DDS phase increment D19 D18 DDS phase increment D18 D17 DDS phase increment D17 D16 DDS phase increment D1...

Page 39: ...D6 DDS phase increment D6 D5 DDS phase increment D5 D4 DDS phase increment D4 D3 DDS phase increment D3 D2 DDS phase increment D2 D1 DDS phase increment D1 D0 DDS phase increment D0 lsb Page 35 Register Description xrm dac d4 1g manual_v2_2 pdf ...

Page 40: ...29 DDS phase increment D29 D28 DDS phase increment D28 D27 DDS phase increment D27 D26 DDS phase increment D26 D25 DDS phase increment D25 D24 DDS phase increment D24 D23 to D16 D23 DDS phase increment D23 D22 DDS phase increment D22 D21 DDS phase increment D21 D20 DDS phase increment D20 D19 DDS phase increment D19 D18 DDS phase increment D18 D17 DDS phase increment D17 D16 DDS phase increment D1...

Page 41: ...D6 DDS phase increment D6 D5 DDS phase increment D5 D4 DDS phase increment D4 D3 DDS phase increment D3 D2 DDS phase increment D2 D1 DDS phase increment D1 D0 DDS phase increment D0 lsb Page 37 Register Description xrm dac d4 1g manual_v2_2 pdf ...

Page 42: ... zero crossing positive slope D30 Triangle start value D14 D29 Triangle start value D13 D28 Triangle start value D12 D27 Triangle start value D11 D26 Triangle start value D10 D25 Triangle start value D9 D24 Triangle start value D8 D23 to D16 D23 Triangle start value D7 D22 Triangle start value D6 D21 Triangle start value D5 D20 Triangle start value D4 D19 Triangle start value D3 D18 Triangle start...

Page 43: ... D6 Ramp increment Triangle end value D6 D5 Ramp increment Triangle end value D5 D4 Ramp increment Triangle end value D4 D3 Ramp increment Triangle end value D3 D2 Ramp increment Triangle end value D2 D1 Ramp increment Triangle end value D1 D0 Ramp increment Triangle end value D0 lsb Page 39 Register Description xrm dac d4 1g manual_v2_2 pdf ...

Page 44: ... zero crossing positive slope D30 Triangle start value D14 D29 Triangle start value D13 D28 Triangle start value D12 D27 Triangle start value D11 D26 Triangle start value D10 D25 Triangle start value D9 D24 Triangle start value D8 D23 to D16 D23 Triangle start value D7 D22 Triangle start value D6 D21 Triangle start value D5 D20 Triangle start value D4 D19 Triangle start value D3 D18 Triangle start...

Page 45: ... D6 Ramp increment Triangle end value D6 D5 Ramp increment Triangle end value D5 D4 Ramp increment Triangle end value D4 D3 Ramp increment Triangle end value D3 D2 Ramp increment Triangle end value D2 D1 Ramp increment Triangle end value D1 D0 Ramp increment Triangle end value D0 lsb Page 41 Register Description xrm dac d4 1g manual_v2_2 pdf ...

Page 46: ...synth serial busy signal Copy of status reg bit 4 D23 to D16 D23 D7 serial read data from the synth interface following a read cycle read only D22 D6 serial read data D21 D5 serial read data D20 D4 serial read data D19 D3 serial read data D18 D2 serial read data D17 D1 serial read data D16 D0 serial read data D15 to D8 D15 D7 serial address for serial read writes of the synth interface D14 D6 seri...

Page 47: ...G User Guide V2 2 Mar 8 2018 D7 to D0 D4 D4 serial write data D3 D3 serial write data D2 D2 serial write data D1 D1 serial write data D0 D0 serial write data Page 43 Register Description xrm dac d4 1g manual_v2_2 pdf ...

Page 48: ...used D20 unused D19 unused D18 unused D17 unused D16 unused D15 to D8 D15 unused D14 unused D13 unused D12 unused D11 unused D10 unused D9 unused D8 unused D7 to D0 D7 Unused D6 Unused D5 Unused D4 Unused D3 Unused D2 Init strobe setting this bit high triggers a synthesiser serial interface initialisation write sequence This bit is self clearing Page 44 Register Description xrm dac d4 1g manual_v2...

Page 49: ...triggers a synthesiser serial interface write cycle using the values in the control register This bit is self clearing D0 Read strobe setting this bit high triggers a synthesiser serial interface read cycle This bit is self clearing Page 45 Register Description xrm dac d4 1g manual_v2_2 pdf ...

Page 50: ...ial busy signal Copy of status reg bit 4 D23 to D16 D23 D7 serial read data from the IDAC interface following a read cycle read only D22 D6 serial read data D21 D5 serial read data D20 D4 serial read data D19 D3 serial read data D18 D2 serial read data D17 D1 serial read data D16 D0 serial read data D15 to D8 D15 D7 serial address for serial read writes of the IDAC interface D14 D6 serial address ...

Page 51: ...G User Guide V2 2 Mar 8 2018 D7 to D0 D4 D4 serial write data D3 D3 serial write data D2 D2 serial write data D1 D1 serial write data D0 D0 serial write data Page 47 Register Description xrm dac d4 1g manual_v2_2 pdf ...

Page 52: ... to D24 D31 Unused D30 Unused D29 Unused D28 Unused D27 Unused D26 Unused D25 Unused D24 Unused D23 to D16 D23 Unused D22 Unused D21 Unused D20 Unused D19 Unused D18 Unused D17 Unused D16 Unused D15 to D8 D15 Unused D14 Unused D13 Unused D12 Unused D11 Unused D10 Unused D9 Unused D8 Unused D7 to D0 D7 Unused D6 Unused D5 Unused D4 Unused D3 Unused Page 48 Register Description xrm dac d4 1g manual_...

Page 53: ...uence This bit is self clearing D1 Write strobe setting this bit high triggers a IDAC serial interface write cycle using the values in the control register This bit is self clearing D0 Read strobe setting this bit high triggers a IDAC serial interface read cycle This bit is self clearing Page 49 Register Description xrm dac d4 1g manual_v2_2 pdf ...

Page 54: ...ial busy signal Copy of status reg bit 4 D23 to D16 D23 D7 serial read data from the QDAC interface following a read cycle read only D22 D6 serial read data D21 D5 serial read data D20 D4 serial read data D19 D3 serial read data D18 D2 serial read data D17 D1 serial read data D16 D0 serial read data D15 to D8 D15 D7 serial address for serial read writes of the QDAC interface D14 D6 serial address ...

Page 55: ...G User Guide V2 2 Mar 8 2018 D7 to D0 D4 D4 serial write data D3 D3 serial write data D2 D2 serial write data D1 D1 serial write data D0 D0 serial write data Page 51 Register Description xrm dac d4 1g manual_v2_2 pdf ...

Page 56: ... to D24 D31 Unused D30 Unused D29 Unused D28 Unused D27 Unused D26 Unused D25 Unused D24 Unused D23 to D16 D23 Unused D22 Unused D21 Unused D20 Unused D19 Unused D18 Unused D17 Unused D16 Unused D15 to D8 D15 Unused D14 Unused D13 Unused D12 Unused D11 Unused D10 Unused D9 Unused D8 Unused D7 to D0 D7 Unused D6 Unused D5 Unused D4 Unused D3 Unused Page 52 Register Description xrm dac d4 1g manual_...

Page 57: ...uence This bit is self clearing D1 Write strobe setting this bit high triggers a QDAC serial interface write cycle using the values in the control register This bit is self clearing D0 Read strobe setting this bit high triggers a QDAC serial interface read cycle This bit is self clearing Page 53 Register Description xrm dac d4 1g manual_v2_2 pdf ...

Page 58: ...CDLL configuration D6 D29 QDACDLL configuration D5 D28 QDACDLL configuration D4 D27 QDACDLL configuration D3 D26 QDACDLL configuration D2 D25 QDACDLL configuration D1 D24 QDACDLL configuration D0 D23 to D16 D23 IDACDLL configuration D7 byte inserted into initialisation sequence triggered by strobe bit D22 IDACDLL configuration D6 D21 IDACDLL configuration D5 D20 IDACDLL configuration D4 D19 IDACDL...

Page 59: ...e code D3 D2 I channel DAC type code D2 D1 I channel DAC type code D1 D0 I channel DAC type code D0 Legal values for the DAC type bits read via serial interface from DAC register CONFIG0 bits D4 D2 inclusive are DAC Type Device ID Device Code DAC5681 111 0x02 DAC5681Z 010 0x04 DAC5682Z 000 0x03 Page 55 Register Description xrm dac d4 1g manual_v2_2 pdf ...

Page 60: ...e RegVal is the register setting D31 to D24 D31 D31 DDS phase msb D30 D30 DDS phase bit D29 D29 DDS phase bit D28 D28 DDS phase bit D27 D27 DDS phase bit D26 D26 DDS phase bit D25 D25 DDS phase bit D24 D24 DDS phase bit D23 to D16 D23 D23 DDS phase bit D22 D22 DDS phase bit D21 D21 DDS phase bit D20 D20 DDS phase bit D19 D19 DDS phase bit D18 D18 DDS phase bit D17 D17 DDS phase bit D16 D16 DDS pha...

Page 61: ...uide V2 2 Mar 8 2018 D6 D6 DDS phase bit D5 D5 DDS phase bit D4 D4 DDS phase bit D3 D3 DDS phase bit D2 D2 DDS phase bit D1 D1 DDS phase bit D0 D0 DDS phase bit lsb Page 57 Register Description xrm dac d4 1g manual_v2_2 pdf ...

Page 62: ...e RegVal is the register setting D31 to D24 D31 D31 DDS phase msb D30 D30 DDS phase bit D29 D29 DDS phase bit D28 D28 DDS phase bit D27 D27 DDS phase bit D26 D26 DDS phase bit D25 D25 DDS phase bit D24 D24 DDS phase bit D23 to D16 D23 D23 DDS phase bit D22 D22 DDS phase bit D21 D21 DDS phase bit D20 D20 DDS phase bit D19 D19 DDS phase bit D18 D18 DDS phase bit D17 D17 DDS phase bit D16 D16 DDS pha...

Page 63: ...uide V2 2 Mar 8 2018 D6 D6 DDS phase bit D5 D5 DDS phase bit D4 D4 DDS phase bit D3 D3 DDS phase bit D2 D2 DDS phase bit D1 D1 DDS phase bit D0 D0 DDS phase bit lsb Page 59 Register Description xrm dac d4 1g manual_v2_2 pdf ...

Page 64: ... are concatenated to specify the 4 sample sequence output during self test operation Other patterns may be used to check individual bits etc D31 to D24 D31 Triangle neg slope bit 15 Pulse Space level bit 15 msb D30 Triangle neg slope bit 14 Pulse Space level bit 14 D29 Triangle neg slope bit 13 Pulse Space level bit 13 D28 Triangle neg slope bit 12 Pulse Space level bit 12 D27 Triangle neg slope b...

Page 65: ...evel bit 8 D7 to D0 D7 Mark level bit 7 Pos slope bit 7 D6 Mark level bit 6 Pos slope bit 6 D5 Mark level bit 5 Pos slope bit 5 D4 Mark level bit 4 Pos slope bit 4 D3 Mark level bit 3 Pos slope bit 3 D2 Mark level bit 2 Pos slope bit 2 D1 Mark level bit 1 Pos slope bit 1 D0 Mark level bit 0 lsb Page 61 Register Description xrm dac d4 1g manual_v2_2 pdf ...

Page 66: ... are concatenated to specify the 4 sample sequence output during self test operation Other patterns may be used to check individual bits etc D31 to D24 D31 Triangle neg slope bit 15 Pulse Space level bit 15 msb D30 Triangle neg slope bit 14 Pulse Space level bit 14 D29 Triangle neg slope bit 13 Pulse Space level bit 13 D28 Triangle neg slope bit 12 Pulse Space level bit 12 D27 Triangle neg slope b...

Page 67: ...evel bit 8 D7 to D0 D7 Mark level bit 7 Pos slope bit 7 D6 Mark level bit 6 Pos slope bit 6 D5 Mark level bit 5 Pos slope bit 5 D4 Mark level bit 4 Pos slope bit 4 D3 Mark level bit 3 Pos slope bit 3 D2 Mark level bit 2 Pos slope bit 2 D1 Mark level bit 1 Pos slope bit 1 D0 Mark level bit 0 lsb Page 63 Register Description xrm dac d4 1g manual_v2_2 pdf ...

Page 68: ...he required sequence D31 to D24 D31 Neg slope bit 15 Space level bit 15 msb D30 Neg slope bit 14 Space level bit 14 D29 Neg slope bit 13 Space level bit 13 D28 Neg slope bit 12 Space level bit 12 D27 Neg slope bit 11 Space level bit 11 D26 Neg slope bit 10 Space level bit 10 D25 Neg slope bit 9 Space level bit 9 D24 Neg slope bit 8 Space level bit 8 D23 to D16 D23 Neg slope bit 7 Space level bit 7...

Page 69: ...XRM 2 DAC D4 1G User Guide V2 2 Mar 8 2018 Note that pulse and triangle periods are constrained to be integer multiples of FABRCLK cycles Page 65 Register Description xrm dac d4 1g manual_v2_2 pdf ...

Page 70: ...he required sequence D31 to D24 D31 Neg slope bit 15 Space level bit 15 msb D30 Neg slope bit 14 Space level bit 14 D29 Neg slope bit 13 Space level bit 13 D28 Neg slope bit 12 Space level bit 12 D27 Neg slope bit 11 Space level bit 11 D26 Neg slope bit 10 Space level bit 10 D25 Neg slope bit 9 Space level bit 9 D24 Neg slope bit 8 Space level bit 8 D23 to D16 D23 Neg slope bit 7 Space level bit 7...

Page 71: ...XRM 2 DAC D4 1G User Guide V2 2 Mar 8 2018 Note that pulse and triangle periods are constrained to be integer multiples of FABRCLK cycles Page 67 Register Description xrm dac d4 1g manual_v2_2 pdf ...

Page 72: ...8 N A D27 N A D26 N A D25 N A D24 N A D23 to D16 D23 D23 gate time multiplier MSB D22 D22 gate time multiplier D21 D21 gate time multiplier D20 D20 gate time multiplier D19 D19 gate time multiplier D18 D18 gate time multiplier D17 D17 gate time multiplier D16 D16 gate time multiplier D15 to D8 D15 D15 gate time multiplier D14 D14 gate time multiplier D13 D13 gate time multiplier D12 D12 gate time ...

Page 73: ... 2018 D7 to D0 D5 D5 gate time multiplier D4 D4 gate time multiplier D3 D3 gate time multiplier D2 D2 gate time multiplier D1 D1 gate time multiplier D0 D0 gate time multiplier LSB Page 69 Register Description xrm dac d4 1g manual_v2_2 pdf ...

Page 74: ... A D27 N A D26 N A D25 N A D24 N A D23 to D16 D23 D23 gate time multiplier MSB D22 D22 gate time multiplier D21 D21 gate time multiplier D20 D20 gate time multiplier D19 D19 gate time multiplier D18 D18 gate time multiplier D17 D17 gate time multiplier D16 D16 gate time multiplier D15 to D8 D15 D15 gate time multiplier D14 D14 gate time multiplier D13 D13 gate time multiplier D12 D12 gate time mul...

Page 75: ... 2018 D7 to D0 D5 D5 gate time multiplier D4 D4 gate time multiplier D3 D3 gate time multiplier D2 D2 gate time multiplier D1 D1 gate time multiplier D0 D0 gate time multiplier LSB Page 71 Register Description xrm dac d4 1g manual_v2_2 pdf ...

Page 76: ... read as 0 D31 to D24 D31 N A D30 N A D29 N A D28 N A D27 N A D26 N A D25 N A D24 N A D23 to D16 D23 N A D22 N A D21 N A D20 N A D19 N A D18 N A D17 N A D16 N A D15 to D8 D15 N A D14 N A D13 N A D12 N A D11 N A D10 N A D9 N A D8 N A D7 to D0 D7 N A D6 N A D5 N A D4 N A D3 N A Page 72 Register Description xrm dac d4 1g manual_v2_2 pdf ...

Page 77: ...XRM 2 DAC D4 1G User Guide V2 2 Mar 8 2018 D7 to D0 D2 N A D1 N A D0 N A Page 73 Register Description xrm dac d4 1g manual_v2_2 pdf ...

Page 78: ...3 to D16 D23 D23 free running counter D22 D22 free running counter D21 D21 free running counter D20 D20 free running counter D19 D19 free running counter D18 D18 free running counter D17 D17 free running counter D16 D16 free running counter D15 to D8 D15 D15 free running counter D14 D14 free running counter D13 D13 free running counter D12 D12 free running counter D11 D11 free running counter D10 ...

Page 79: ...D4 1G User Guide V2 2 Mar 8 2018 D7 to D0 D2 D2 free running counter D1 D1 free running counter D0 D0 free running counter LSB changes at 1 us intervals Page 75 Register Description xrm dac d4 1g manual_v2_2 pdf ...

Page 80: ...t D12 D27 bit D11 D26 bit D10 D25 bit D9 D24 bit D8 D23 to D16 D23 bit D7 of 16 bit sample number N 1 D22 bit D6 D21 bit D5 D20 bit D4 D19 bit D3 D18 bit D2 D17 bit D1 D16 bit D0 LSB of 16 bit sample number N 1 D15 to D8 D15 bit D15 of 16 bit sample number N D14 bit D14 D13 bit D13 D12 bit D12 D11 bit D11 D10 bit D10 D9 N A D8 N A D7 to D0 D7 bit D7 of 16 bit sample number N D6 bit D6 D5 bit D5 D4...

Page 81: ...XRM 2 DAC D4 1G User Guide V2 2 Mar 8 2018 D7 to D0 D2 bit D2 D1 bit D1 D0 D0 LSB of 16 bit sample number N Page 77 Register Description xrm dac d4 1g manual_v2_2 pdf ...

Page 82: ...bit D12 D27 bit D11 D26 bit D10 D25 bit D9 D24 bit D8 D23 to D16 D23 bit D7 of 16 bit sample number N 1 D22 bit D6 D21 bit D5 D20 bit D4 D19 bit D3 D18 bit D2 D17 bit D1 D16 D0 LSB of 16 bit sample number N 1 D15 to D8 D15 bit D15 of 16 bit sample number N D14 bit D14 D13 bit D13 D12 bit D12 D11 bit D11 D10 bit D10 D9 N A D8 N A D7 to D0 D7 bit D7 of 16 bit sample number N D6 bit D6 D5 bit D5 D4 b...

Page 83: ...XRM 2 DAC D4 1G User Guide V2 2 Mar 8 2018 D7 to D0 D2 bit D2 D1 bit D1 D0 D0 LSB of 16 bit sample number N Page 79 Register Description xrm dac d4 1g manual_v2_2 pdf ...

Page 84: ...ngth D20 D4 ARB sequence length D19 D3 ARB sequence length D18 D2 ARB sequence length D17 D1 ARB sequence length D16 LSB of ARB sequence length D15 to D8 D15 QARB tick to AUX port driver mux 1 tick as driver else trigger signal from control register D14 N A D13 N A D12 N A D11 N A D10 Load enable for QARB length value D9 Burst continuous select for QARB sequence D8 Run enable for QARB sequence D7 ...

Page 85: ...4 1G User Guide V2 2 Mar 8 2018 D7 to D0 D2 Load enable for IARB length value D1 Burst continuous select for IARB sequence D0 Run enable for IARB sequence Page 81 Register Description xrm dac d4 1g manual_v2_2 pdf ...

Page 86: ... D13 marker width D28 D12 marker width D27 D11 marker width D26 D10 marker width D25 D9 marker width D24 D8 marker width D23 to D16 D23 D7 marker width D22 D6 marker width D21 D5 marker width D20 D4 marker width D19 D3 marker width D18 D2 marker width D17 D1 marker width D16 ARB sequence marker width LSB D15 to D8 D15 MSB of 16 bit repeat rate control for ARB sequence D14 D14 repeat rate control D...

Page 87: ... Guide V2 2 Mar 8 2018 D7 to D0 D3 D3 repeat rate control D2 D2 repeat rate control D1 D1 repeat rate control D0 LSB of 16 bit repeat rate control for ARB sequence Page 83 Register Description xrm dac d4 1g manual_v2_2 pdf ...

Page 88: ...hannel mark duration fine control bit 1 D20 Q channel mark duration fine control bit 0 lsb D19 Unused D18 I channel mark duration fine control bit 2 msb D17 I channel mark duration fine control bit 1 D16 I channel mark duration fine control bit 0 lsb D15 to D8 D15 Unused D14 Unused D13 Unused D12 Unused D11 Unused D10 Unused D9 Unused D8 Unused D7 to D0 D7 Unused D6 Unused D5 Unused D4 Active high...

Page 89: ...if differing mark space ratios are programmed Note that pulse periods are still constrained to be multiples of FABRCLK cycles Fine Adjust Phase1 Phase2 0 4 spaces 0 mark 1 3 spaces 1 marks 2 2 spaces 2 marks 3 1 spaces 3 marks 4 0 spaces 4 marks 5 1 mark 3 spaces 6 2 marks 2 spaces 7 3 marks 1 space D1 XRM board revision setting this bit high routes DAC data with polarities for rev2 boards setting...

Page 90: ...copy D29 sign bit copy D28 sign bit copy D27 sign bit copy D26 sign bit copy D25 sign bit copy D24 D8 sign and magnitude of width end point of valid DCM phase window D23 to D16 D23 D7 of width end point of valid DCM phase window D22 D6 of width end point of valid DCM phase window D21 D5 of width end point of valid DCM phase window D20 D4 of width end point of valid DCM phase window D19 D3 of width...

Page 91: ...hase window D4 D4 mid point start point of valid DCM phase window D3 D3 mid point start point of valid DCM phase window D2 D2 mid point start point of valid DCM phase window D1 D1 mid point start point of valid DCM phase window D0 D0 mid point start point of valid DCM phase window Page 87 Register Description xrm dac d4 1g manual_v2_2 pdf ...

Page 92: ... 0 Added Virtex7 Kintex7 and Vivado information Added ARB ram signal generation and programmable sine phase descriptions Fixed various typos and added waveform generation description 08 12 17 2 1 Fixed typos and updated waveform generation description 08 03 18 2 2 Modified to be XRM XRM2 manual Address 4 West Silvermills Lane Edinburgh EH3 5BD UK Telephone 44 131 558 2600 Fax 44 131 558 2700 email...

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